/llvm-project/llvm/unittests/Support/ |
H A D | MathExtrasTest.cpp | 101 unsigned MaskIdx, MaskLen; in TEST() local 120 unsigned MaskIdx, MaskLen; in TEST() local [all...] |
/llvm-project/llvm/include/llvm/Support/ |
H A D | MathExtras.h | 306 isShiftedMask_32(uint32_t Value,unsigned & MaskIdx,unsigned & MaskLen) isShiftedMask_32() argument 319 isShiftedMask_64(uint64_t Value,unsigned & MaskIdx,unsigned & MaskLen) isShiftedMask_64() argument
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/llvm-project/llvm/include/llvm/ADT/ |
H A D | APInt.h | 502 isShiftedMask(unsigned & MaskIdx,unsigned & MaskLen) isShiftedMask() argument
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/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstCombineIntrinsic.cpp | 2216 unsigned MaskIdx, MaskLen; instCombineIntrinsic() local 2260 unsigned MaskIdx, MaskLen; instCombineIntrinsic() local
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H A D | X86ISelDAGToDAG.cpp | 2188 unsigned MaskIdx, MaskLen; foldMaskAndShiftToScale() local 2287 unsigned MaskIdx, MaskLen; foldMaskedShiftToBEXTR() local
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/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchISelLowering.cpp | 2295 unsigned MaskIdx, MaskLen; performSRLCombine() local 2456 unsigned MaskIdx, MaskLen; performORCombine() local [all...] |
/llvm-project/llvm/unittests/ADT/ |
H A D | APIntTest.cpp | 1796 unsigned MaskIdx, MaskLen; TEST() local [all...] |
/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAGHVX.cpp | 1086 unsigned MaskLen = SM.Mask.size(); getOutputSegmentMap() local
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/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 749 unsigned LowZBits, MaskLen; SelectShiftedRegisterFromAnd() local
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H A D | AArch64ISelLowering.cpp | 16092 unsigned MaskLen = NumElts * Factor; createTblShuffleMask() local 17326 unsigned MaskIdx, MaskLen; isDesirableToCommuteXorWithShift() local [all...] |
/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 4114 unsigned MaskIdx, MaskLen; performSrlCombine() local
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/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 13865 unsigned MaskIdx, MaskLen; isDesirableToCommuteXorWithShift() local
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