| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 46 Register llvm::constrainRegToClass(MachineRegisterInfo &MRI, in constrainRegToClass() argument
58 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass() argument
110 MachineRegisterInfo &MRI, cons in constrainOperandRegClass() argument
163 MachineRegisterInfo &MRI = MF.getRegInfo(); constrainSelectedInstRegOperands() local
202 canReplaceReg(Register DstReg,Register SrcReg,MachineRegisterInfo & MRI) canReplaceReg() argument
223 isTriviallyDead(const MachineInstr & MI,const MachineRegisterInfo & MRI) isTriviallyDead() argument
296 getIConstantVRegVal(Register VReg,const MachineRegisterInfo & MRI) getIConstantVRegVal() argument
307 getIConstantVRegSExtVal(Register VReg,const MachineRegisterInfo & MRI) getIConstantVRegSExtVal() argument
329 getConstantVRegValWithLookThrough(Register VReg,const MachineRegisterInfo & MRI,bool LookThroughInstrs=true,bool LookThroughAnyExt=false) getConstantVRegValWithLookThrough() argument
427 getIConstantVRegValWithLookThrough(Register VReg,const MachineRegisterInfo & MRI,bool LookThroughInstrs) getIConstantVRegValWithLookThrough() argument
433 getAnyConstantVRegValWithLookThrough(Register VReg,const MachineRegisterInfo & MRI,bool LookThroughInstrs,bool LookThroughAnyExt) getAnyConstantVRegValWithLookThrough() argument
441 getFConstantVRegValWithLookThrough(Register VReg,const MachineRegisterInfo & MRI,bool LookThroughInstrs) getFConstantVRegValWithLookThrough() argument
452 getConstantFPVRegVal(Register VReg,const MachineRegisterInfo & MRI) getConstantFPVRegVal() argument
460 getDefSrcRegIgnoringCopies(Register Reg,const MachineRegisterInfo & MRI) getDefSrcRegIgnoringCopies() argument
480 getDefIgnoringCopies(Register Reg,const MachineRegisterInfo & MRI) getDefIgnoringCopies() argument
487 getSrcRegIgnoringCopies(Register Reg,const MachineRegisterInfo & MRI) getSrcRegIgnoringCopies() argument
496 extractParts(Register Reg,LLT Ty,int NumParts,SmallVectorImpl<Register> & VRegs,MachineIRBuilder & MIRBuilder,MachineRegisterInfo & MRI) extractParts() argument
506 extractParts(Register Reg,LLT RegTy,LLT MainTy,LLT & LeftoverTy,SmallVectorImpl<Register> & VRegs,SmallVectorImpl<Register> & LeftoverRegs,MachineIRBuilder & MIRBuilder,MachineRegisterInfo & MRI) extractParts() argument
600 extractVectorParts(Register Reg,unsigned NumElts,SmallVectorImpl<Register> & VRegs,MachineIRBuilder & MIRBuilder,MachineRegisterInfo & MRI) extractVectorParts() argument
640 getOpcodeDef(unsigned Opcode,Register Reg,const MachineRegisterInfo & MRI) getOpcodeDef() argument
661 ConstantFoldBinOp(unsigned Opcode,const Register Op1,const Register Op2,const MachineRegisterInfo & MRI) ConstantFoldBinOp() argument
728 ConstantFoldFPBinOp(unsigned Opcode,const Register Op1,const Register Op2,const MachineRegisterInfo & MRI) ConstantFoldFPBinOp() argument
783 ConstantFoldVectorBinop(unsigned Opcode,const Register Op1,const Register Op2,const MachineRegisterInfo & MRI) ConstantFoldVectorBinop() argument
803 isKnownNeverNaN(Register Val,const MachineRegisterInfo & MRI,bool SNaN) isKnownNeverNaN() argument
903 MachineRegisterInfo &MRI = MF.getRegInfo(); getFunctionLiveInPhysReg() local
932 ConstantFoldExtOp(unsigned Opcode,const Register Op1,uint64_t Imm,const MachineRegisterInfo & MRI) ConstantFoldExtOp() argument
949 ConstantFoldCastOp(unsigned Opcode,LLT DstTy,const Register Op0,const MachineRegisterInfo & MRI) ConstantFoldCastOp() argument
972 ConstantFoldIntToFloat(unsigned Opcode,LLT DstTy,Register Src,const MachineRegisterInfo & MRI) ConstantFoldIntToFloat() argument
984 ConstantFoldCountZeros(Register Src,const MachineRegisterInfo & MRI,std::function<unsigned (APInt)> CB) ConstantFoldCountZeros() argument
1017 ConstantFoldICmp(unsigned Pred,const Register Op1,const Register Op2,const MachineRegisterInfo & MRI) ConstantFoldICmp() argument
1083 isKnownToBeAPowerOfTwo(Register Reg,const MachineRegisterInfo & MRI,GISelKnownBits * KB) isKnownToBeAPowerOfTwo() argument
1330 getAnyConstantSplat(Register VReg,const MachineRegisterInfo & MRI,bool AllowUndef) getAnyConstantSplat() argument
1372 isBuildVectorConstantSplat(const Register Reg,const MachineRegisterInfo & MRI,int64_t SplatValue,bool AllowUndef) isBuildVectorConstantSplat() argument
1380 isBuildVectorConstantSplat(const MachineInstr & MI,const MachineRegisterInfo & MRI,int64_t SplatValue,bool AllowUndef) isBuildVectorConstantSplat() argument
1387 getIConstantSplatVal(const Register Reg,const MachineRegisterInfo & MRI) getIConstantSplatVal() argument
1400 getIConstantSplatVal(const MachineInstr & MI,const MachineRegisterInfo & MRI) getIConstantSplatVal() argument
1406 getIConstantSplatSExtVal(const Register Reg,const MachineRegisterInfo & MRI) getIConstantSplatSExtVal() argument
1415 getIConstantSplatSExtVal(const MachineInstr & MI,const MachineRegisterInfo & MRI) getIConstantSplatSExtVal() argument
1420 getFConstantSplat(Register VReg,const MachineRegisterInfo & MRI,bool AllowUndef) getFConstantSplat() argument
1428 isBuildVectorAllZeros(const MachineInstr & MI,const MachineRegisterInfo & MRI,bool AllowUndef) isBuildVectorAllZeros() argument
1434 isBuildVectorAllOnes(const MachineInstr & MI,const MachineRegisterInfo & MRI,bool AllowUndef) isBuildVectorAllOnes() argument
1440 getVectorSplat(const MachineInstr & MI,const MachineRegisterInfo & MRI) getVectorSplat() argument
1454 isConstantScalar(const MachineInstr & MI,const MachineRegisterInfo & MRI,bool AllowFP=true,bool AllowOpaqueConstants=true) isConstantScalar() argument
1474 isConstantOrConstantVector(MachineInstr & MI,const MachineRegisterInfo & MRI) isConstantOrConstantVector() argument
1491 isConstantOrConstantVector(const MachineInstr & MI,const MachineRegisterInfo & MRI,bool AllowFP,bool AllowOpaqueConstants) isConstantOrConstantVector() argument
1511 isConstantOrConstantSplatVector(MachineInstr & MI,const MachineRegisterInfo & MRI) isConstantOrConstantSplatVector() argument
1523 isNullOrNullSplat(const MachineInstr & MI,const MachineRegisterInfo & MRI,bool AllowUndefs) isNullOrNullSplat() argument
1541 isAllOnesOrAllOnesSplat(const MachineInstr & MI,const MachineRegisterInfo & MRI,bool AllowUndefs) isAllOnesOrAllOnesSplat() argument
1556 matchUnaryPredicate(const MachineRegisterInfo & MRI,Register Reg,std::function<bool (const Constant * ConstVal)> Match,bool AllowUndefs) matchUnaryPredicate() argument
1631 saveUsesAndErase(MachineInstr & MI,MachineRegisterInfo & MRI,LostDebugLocObserver * LocObserver,SmallInstListTy & DeadInstChain) saveUsesAndErase() argument
1646 eraseInstrs(ArrayRef<MachineInstr * > DeadInstrs,MachineRegisterInfo & MRI,LostDebugLocObserver * LocObserver) eraseInstrs() argument
1660 eraseInstr(MachineInstr & MI,MachineRegisterInfo & MRI,LostDebugLocObserver * LocObserver) eraseInstr() argument
1665 salvageDebugInfo(const MachineRegisterInfo & MRI,MachineInstr & MI) salvageDebugInfo() argument
1731 shiftAmountKnownInRange(Register ShiftAmount,const MachineRegisterInfo & MRI) shiftAmountKnownInRange() argument
1778 canCreateUndefOrPoison(Register Reg,const MachineRegisterInfo & MRI,bool ConsiderFlagsAndMetadata,UndefPoisonKind Kind) canCreateUndefOrPoison() argument
1838 isGuaranteedNotToBeUndefOrPoison(Register Reg,const MachineRegisterInfo & MRI,unsigned Depth,UndefPoisonKind Kind) isGuaranteedNotToBeUndefOrPoison() argument
1877 canCreateUndefOrPoison(Register Reg,const MachineRegisterInfo & MRI,bool ConsiderFlagsAndMetadata) canCreateUndefOrPoison() argument
1883 canCreatePoison(Register Reg,const MachineRegisterInfo & MRI,bool ConsiderFlagsAndMetadata=true) canCreatePoison() argument
1890 isGuaranteedNotToBeUndefOrPoison(Register Reg,const MachineRegisterInfo & MRI,unsigned Depth) isGuaranteedNotToBeUndefOrPoison() argument
1897 isGuaranteedNotToBePoison(Register Reg,const MachineRegisterInfo & MRI,unsigned Depth) isGuaranteedNotToBePoison() argument
1904 isGuaranteedNotToBeUndef(Register Reg,const MachineRegisterInfo & MRI,unsigned Depth) isGuaranteedNotToBeUndef() argument
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64GlobalISelUtils.cpp | 22 getAArch64VectorSplat(const MachineInstr & MI,const MachineRegisterInfo & MRI) getAArch64VectorSplat() argument
36 getAArch64VectorSplatScalar(const MachineInstr & MI,const MachineRegisterInfo & MRI) getAArch64VectorSplatScalar() argument
45 isCMN(const MachineInstr * MaybeSub,const CmpInst::Predicate & Pred,const MachineRegisterInfo & MRI) isCMN() argument
67 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); tryEmitBZero() local
101 extractPtrauthBlendDiscriminators(Register Disc,MachineRegisterInfo & MRI) extractPtrauthBlendDiscriminators() argument
[all...] |
| H A D | AArch64PostLegalizerLowering.cpp | 157 matchREV(MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchREV() argument
193 matchTRN(MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchTRN() argument
214 matchUZP(MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchUZP() argument
230 matchZip(MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchZip() argument
248 matchDupFromInsertVectorElt(int Lane,MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchDupFromInsertVectorElt() argument
288 matchDupFromBuildVector(int Lane,MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchDupFromBuildVector() argument
303 matchDup(MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchDup() argument
349 matchEXT(MachineInstr & MI,MachineRegisterInfo & MRI,ShuffleVectorPseudo & MatchInfo) matchEXT() argument
405 matchNonConstInsert(MachineInstr & MI,MachineRegisterInfo & MRI) matchNonConstInsert() argument
413 applyNonConstInsert(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & Builder) applyNonConstInsert() argument
465 matchINS(MachineInstr & MI,MachineRegisterInfo & MRI,std::tuple<Register,int,Register,int> & MatchInfo) matchINS() argument
492 applyINS(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & Builder,std::tuple<Register,int,Register,int> & MatchInfo) applyINS() argument
511 isVShiftRImm(Register Reg,MachineRegisterInfo & MRI,LLT Ty,int64_t & Cnt) isVShiftRImm() argument
524 matchVAshrLshrImm(MachineInstr & MI,MachineRegisterInfo & MRI,int64_t & Imm) matchVAshrLshrImm() argument
534 applyVAshrLshrImm(MachineInstr & MI,MachineRegisterInfo & MRI,int64_t & Imm) applyVAshrLshrImm() argument
555 tryAdjustICmpImmAndPred(Register RHS,CmpInst::Predicate P,const MachineRegisterInfo & MRI) tryAdjustICmpImmAndPred() argument
663 matchAdjustICmpImmAndPred(MachineInstr & MI,const MachineRegisterInfo & MRI,std::pair<uint64_t,CmpInst::Predicate> & MatchInfo) matchAdjustICmpImmAndPred() argument
680 MachineRegisterInfo &MRI = *MIB.getMRI(); applyAdjustICmpImmAndPred() local
689 matchDupLane(MachineInstr & MI,MachineRegisterInfo & MRI,std::pair<unsigned,int> & MatchInfo) matchDupLane() argument
745 applyDupLane(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,std::pair<unsigned,int> & MatchInfo) applyDupLane() argument
767 matchScalarizeVectorUnmerge(MachineInstr & MI,MachineRegisterInfo & MRI) matchScalarizeVectorUnmerge() argument
777 applyScalarizeVectorUnmerge(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B) applyScalarizeVectorUnmerge() argument
790 matchBuildVectorToDup(MachineInstr & MI,MachineRegisterInfo & MRI) matchBuildVectorToDup() argument
804 applyBuildVectorToDup(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B) applyBuildVectorToDup() argument
814 getCmpOperandFoldingProfit(Register CmpOp,MachineRegisterInfo & MRI) getCmpOperandFoldingProfit() argument
868 trySwapICmpOperands(MachineInstr & MI,MachineRegisterInfo & MRI) trySwapICmpOperands() argument
921 getVectorFCMP(AArch64CC::CondCode CC,Register LHS,Register RHS,bool IsZero,bool NoNans,MachineRegisterInfo & MRI) getVectorFCMP() argument
974 matchLowerVectorFCMP(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & MIB) matchLowerVectorFCMP() argument
994 applyLowerVectorFCMP(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & MIB) applyLowerVectorFCMP() argument
1051 matchFormTruncstore(MachineInstr & MI,MachineRegisterInfo & MRI,Register & SrcReg) matchFormTruncstore() argument
1064 applyFormTruncstore(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer,Register & SrcReg) applyFormTruncstore() argument
1076 matchVectorSextInReg(MachineInstr & MI,MachineRegisterInfo & MRI) matchVectorSextInReg() argument
1083 applyVectorSextInReg(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer) applyVectorSextInReg() argument
1093 matchUnmergeExtToUnmerge(MachineInstr & MI,MachineRegisterInfo & MRI,Register & MatchInfo) matchUnmergeExtToUnmerge() argument
1123 applyUnmergeExtToUnmerge(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer,Register & SrcReg) applyUnmergeExtToUnmerge() argument
1140 matchExtMulToMULL(MachineInstr & MI,MachineRegisterInfo & MRI) matchExtMulToMULL() argument
1166 applyExtMulToMULL(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer) applyExtMulToMULL() argument
[all...] |
| H A D | AArch64PostLegalizerCombiner.cpp | 67 MachineInstr &MI, MachineRegisterInfo &MRI, in matchExtractVecEltPairwiseAdd() argument
110 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilde in applyExtractVecEltPairwiseAdd() argument
125 isSignExtended(Register R,MachineRegisterInfo & MRI) isSignExtended() argument
131 isZeroExtended(Register R,MachineRegisterInfo & MRI) isZeroExtended() argument
137 matchAArch64MulConstCombine(MachineInstr & MI,MachineRegisterInfo & MRI,std::function<void (MachineIRBuilder & B,Register DstReg)> & ApplyFn) matchAArch64MulConstCombine() argument
250 applyAArch64MulConstCombine(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,std::function<void (MachineIRBuilder & B,Register DstReg)> & ApplyFn) applyAArch64MulConstCombine() argument
259 matchFoldMergeToZext(MachineInstr & MI,MachineRegisterInfo & MRI) matchFoldMergeToZext() argument
267 applyFoldMergeToZext(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer) applyFoldMergeToZext() argument
280 matchMutateAnyExtToZExt(MachineInstr & MI,MachineRegisterInfo & MRI) matchMutateAnyExtToZExt() argument
297 applyMutateAnyExtToZExt(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer) applyMutateAnyExtToZExt() argument
307 matchSplitStoreZero128(MachineInstr & MI,MachineRegisterInfo & MRI) matchSplitStoreZero128() argument
325 applySplitStoreZero128(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,GISelChangeObserver & Observer) applySplitStoreZero128() argument
345 matchOrToBSP(MachineInstr & MI,MachineRegisterInfo & MRI,std::tuple<Register,Register,Register> & MatchInfo) matchOrToBSP() argument
376 applyOrToBSP(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,std::tuple<Register,Register,Register> & MatchInfo) applyOrToBSP() argument
387 matchCombineMulCMLT(MachineInstr & MI,MachineRegisterInfo & MRI,Register & SrcReg) matchCombineMulCMLT() argument
422 applyCombineMulCMLT(MachineInstr & MI,MachineRegisterInfo & MRI,MachineIRBuilder & B,Register & SrcReg) applyCombineMulCMLT() argument
597 auto &MRI = MIB.getMF().getRegInfo(); tryOptimizeConsecStores() local
649 auto &MRI = MF.getRegInfo(); optimizeConsecutiveMemOpAddressing() local
[all...] |
| H A D | AArch64InstructionSelector.cpp | 739 auto &MRI = MF.getRegInfo(); getImmedFromMO() local
764 unsupportedBinOp(const MachineInstr & I,const AArch64RegisterBankInfo & RBI,const MachineRegisterInfo & MRI,const AArch64RegisterInfo & TRI) unsupportedBinOp() argument
917 copySubReg(MachineInstr & I,MachineRegisterInfo & MRI,const RegisterBankInfo & RBI,Register SrcReg,const TargetRegisterClass * To,unsigned SubReg) copySubReg() argument
944 getRegClassesForCopy(MachineInstr & I,const TargetInstrInfo & TII,MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,const RegisterBankInfo & RBI) getRegClassesForCopy() argument
972 selectDebugInstr(MachineInstr & I,MachineRegisterInfo & MRI,const RegisterBankInfo & RBI) selectDebugInstr() argument
1002 selectCopy(MachineInstr & I,const TargetInstrInfo & TII,MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,const RegisterBankInfo & RBI) selectCopy() argument
1172 MachineRegisterInfo &MRI = *MIB.getMRI(); emitSelect() local
1452 getTestBitReg(Register Reg,uint64_t & Bit,bool & Invert,MachineRegisterInfo & MRI) getTestBitReg() argument
1588 MachineRegisterInfo &MRI = *MIB.getMRI(); emitTestBit() local
1661 MachineRegisterInfo &MRI = *MIB.getMRI(); emitCBZ() local
1708 MachineRegisterInfo &MRI = *MIB.getMRI(); tryOptCompareBranchFedByICmp() local
1810 selectCompareBranch(MachineInstr & I,MachineFunction & MF,MachineRegisterInfo & MRI) selectCompareBranch() argument
1845 getVectorShiftImm(Register Reg,MachineRegisterInfo & MRI) getVectorShiftImm() argument
1854 getVectorSHLImm(LLT SrcTy,Register Reg,MachineRegisterInfo & MRI) getVectorSHLImm() argument
1887 selectVectorSHL(MachineInstr & I,MachineRegisterInfo & MRI) selectVectorSHL() argument
1932 selectVectorAshrLshr(MachineInstr & I,MachineRegisterInfo & MRI) selectVectorAshrLshr() argument
2034 MachineRegisterInfo &MRI = MF.getRegInfo(); materializeLargeCMVal() local
2070 MachineRegisterInfo &MRI = MF.getRegInfo(); preISelLower() local
2149 convertPtrAddToAdd(MachineInstr & I,MachineRegisterInfo & MRI) convertPtrAddToAdd() argument
2187 earlySelectSHL(MachineInstr & I,MachineRegisterInfo & MRI) earlySelectSHL() argument
2221 contractCrossBankCopyIntoStore(MachineInstr & I,MachineRegisterInfo & MRI) contractCrossBankCopyIntoStore() argument
2268 MachineRegisterInfo &MRI = MF.getRegInfo(); earlySelect() local
2439 MachineRegisterInfo &MRI = MF.getRegInfo(); select() local
3536 selectMOPS(MachineInstr & GI,MachineRegisterInfo & MRI) selectMOPS() argument
3594 selectBrJT(MachineInstr & I,MachineRegisterInfo & MRI) selectBrJT() argument
3617 selectJumpTable(MachineInstr & I,MachineRegisterInfo & MRI) selectJumpTable() argument
3633 selectTLSGlobalValue(MachineInstr & I,MachineRegisterInfo & MRI) selectTLSGlobalValue() argument
3723 selectMergeValues(MachineInstr & I,MachineRegisterInfo & MRI) selectMergeValues() argument
3823 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); emitExtractVectorElt() local
3881 selectExtractElt(MachineInstr & I,MachineRegisterInfo & MRI) selectExtractElt() argument
3920 selectSplitVectorUnmerge(MachineInstr & I,MachineRegisterInfo & MRI) selectSplitVectorUnmerge() argument
3948 selectUnmergeValues(MachineInstr & I,MachineRegisterInfo & MRI) selectUnmergeValues() argument
4068 selectConcatVectors(MachineInstr & I,MachineRegisterInfo & MRI) selectConcatVectors() argument
4206 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); emitAddSub() local
4281 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); emitADCS() local
4292 MachineRegisterInfo *MRI = MIRBuilder.getMRI(); emitSBCS() local
4301 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); emitCMN() local
4311 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); emitTST() local
4341 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); emitIntegerCompare() local
4356 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); emitCSetForFCmp() local
4383 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); emitFPCompare() local
4430 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); emitVectorConcat() local
4487 auto &MRI = *MIRBuilder.getMRI(); emitCSINC() local
4507 MachineRegisterInfo *MRI = MIB.getMRI(); emitCarryIn() local
4548 selectOverflowOp(MachineInstr & I,MachineRegisterInfo & MRI) selectOverflowOp() argument
4619 canEmitConjunction(Register Val,bool & CanNegate,bool & MustBeFirst,bool WillNegate,MachineRegisterInfo & MRI,unsigned Depth=0) canEmitConjunction() argument
4675 auto &MRI = *MIB.getMRI(); emitConditionalComparison() local
4725 auto &MRI = *MIB.getMRI(); emitConjunctionRec() local
4858 MachineRegisterInfo &MRI = *MIB.getMRI(); tryOptSelect() local
4939 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); tryFoldIntegerCompare() local
5000 selectShuffleVector(MachineInstr & I,MachineRegisterInfo & MRI) selectShuffleVector() argument
5085 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); emitLaneInsert() local
5111 selectUSMovFromExtend(MachineInstr & MI,MachineRegisterInfo & MRI) selectUSMovFromExtend() argument
5345 selectIndexedExtLoad(MachineInstr & MI,MachineRegisterInfo & MRI) selectIndexedExtLoad() argument
5432 selectIndexedLoad(MachineInstr & MI,MachineRegisterInfo & MRI) selectIndexedLoad() argument
5481 selectIndexedStore(GIndexedStore & I,MachineRegisterInfo & MRI) selectIndexedStore() argument
5530 emitConstantVector(Register Dst,Constant * CV,MachineIRBuilder & MIRBuilder,MachineRegisterInfo & MRI) emitConstantVector() argument
5625 tryOptConstantBuildVec(MachineInstr & I,LLT DstTy,MachineRegisterInfo & MRI) tryOptConstantBuildVec() argument
5656 tryOptBuildVecToSubregToReg(MachineInstr & I,MachineRegisterInfo & MRI) tryOptBuildVecToSubregToReg() argument
5694 selectBuildVector(MachineInstr & I,MachineRegisterInfo & MRI) selectBuildVector() argument
5798 auto &MRI = *MIB.getMRI(); selectVectorLoadIntrinsic() local
5826 auto &MRI = *MIB.getMRI(); selectVectorLoadLaneIntrinsic() local
5877 MachineRegisterInfo &MRI = I.getParent()->getParent()->getRegInfo(); selectVectorStoreIntrinsic() local
5894 MachineRegisterInfo &MRI = I.getParent()->getParent()->getRegInfo(); selectVectorStoreLaneIntrinsic() local
5925 selectIntrinsicWithSideEffects(MachineInstr & I,MachineRegisterInfo & MRI) selectIntrinsicWithSideEffects() argument
6453 selectIntrinsic(MachineInstr & I,MachineRegisterInfo & MRI) selectIntrinsic() argument
6732 SelectTable(MachineInstr & I,MachineRegisterInfo & MRI,unsigned NumVec,unsigned Opc1,unsigned Opc2,bool isExt) SelectTable() argument
6852 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); selectNegArithImmed() local
6904 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); selectExtendedSHL() local
7016 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); selectAddrModeShiftedExtendXReg() local
7055 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); selectAddrModeRegisterOffset() local
7088 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); selectAddrModeXRO() local
7162 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo(); selectAddrModeWRO() local
7229 MachineRegisterInfo &MRI = selectAddrModeUnscaled() local
7303 MachineRegisterInfo &MRI = MF.getRegInfo(); selectAddrModeIndexed() local
7381 MachineRegisterInfo &MRI = selectShiftedRegister() local
7415 getExtendTypeForInst(MachineInstr & MI,MachineRegisterInfo & MRI,bool IsLoadStore) const getExtendTypeForInst() argument
7476 MachineRegisterInfo &MRI = *MIB.getMRI(); moveScalarRegClass() local
7496 MachineRegisterInfo &MRI = selectArithExtendedRegister() local
7561 MachineRegisterInfo &MRI = selectExtractHigh() local
7595 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); renderTruncImm() local
7678 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); isDef32() local
7700 fixupPHIOpBanks(MachineInstr & MI,MachineRegisterInfo & MRI,const AArch64RegisterBankInfo & RBI) fixupPHIOpBanks() argument
7735 MachineRegisterInfo &MRI = MF.getRegInfo(); processPHIs() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAsmBackendDarwin.h | 19 const MCRegisterInfo &MRI; variable
24 const MCRegisterInfo &MRI) in ARMAsmBackendDarwin() argument
|
| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchOptWInstrs.cpp | 100 const MachineRegisterInfo &MRI, unsigned OrigBits) { in hasAllNBitUsers() argument
317 hasAllWUsers(const MachineInstr & OrigMI,const LoongArchSubtarget & ST,const MachineRegisterInfo & MRI) hasAllWUsers() argument
324 isSignExtendingOpW(const MachineInstr & MI,const MachineRegisterInfo & MRI,unsigned OpNo) isSignExtendingOpW() argument
478 isSignExtendedW(Register SrcReg,const LoongArchSubtarget & ST,const MachineRegisterInfo & MRI,SmallPtrSetImpl<MachineInstr * > & FixableDef) isSignExtendedW() argument
671 removeSExtWInstrs(MachineFunction & MF,const LoongArchInstrInfo & TII,const LoongArchSubtarget & ST,MachineRegisterInfo & MRI) removeSExtWInstrs() argument
723 convertToDSuffixes(MachineFunction & MF,const LoongArchInstrInfo & TII,const LoongArchSubtarget & ST,MachineRegisterInfo & MRI) convertToDSuffixes() argument
749 convertToWSuffixes(MachineFunction & MF,const LoongArchInstrInfo & TII,const LoongArchSubtarget & ST,MachineRegisterInfo & MRI) convertToWSuffixes() argument
802 MachineRegisterInfo &MRI = MF.getRegInfo(); runOnMachineFunction() local
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCCallLowering.h | 42 MachineRegisterInfo &MRI) in PPCIncomingValueHandler()
67 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI) in FormalArgHandler()
|
| H A D | PPCRegisterBankInfo.cpp | 83 const MachineRegisterInfo &MRI = MF.getRegInfo(); getInstrMapping() local
252 hasFPConstraints(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const hasFPConstraints() argument
295 onlyUsesFP(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const onlyUsesFP() argument
314 onlyDefinesFP(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const onlyDefinesFP() argument
[all...] |
| /llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86RegisterBankInfo.cpp | 75 isFPIntrinsic(const MachineRegisterInfo & MRI,const MachineInstr & MI) isFPIntrinsic() argument
96 hasFPConstraints(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const hasFPConstraints() argument
134 onlyUsesFP(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const onlyUsesFP() argument
153 onlyDefinesFP(const MachineInstr & MI,const MachineRegisterInfo & MRI,const TargetRegisterInfo & TRI,unsigned Depth) const onlyDefinesFP() argument
223 getInstrPartialMappingIdxs(const MachineInstr & MI,const MachineRegisterInfo & MRI,const bool isFP,SmallVectorImpl<PartialMappingIdx> & OpRegBankIdx) getInstrPartialMappingIdxs() argument
262 const MachineRegisterInfo &MRI = MF.getRegInfo(); getSameOperandsMapping() local
280 const MachineRegisterInfo &MRI = MF.getRegInfo(); getInstrMapping() local
426 const MachineRegisterInfo &MRI = MF.getRegInfo(); getInstrAlternativeMappings() local
[all...] |
| H A D | X86InstructionSelector.cpp | 351 MachineRegisterInfo &MRI = MF.getRegInfo(); select() local
520 X86SelectAddress(const MachineInstr & I,const MachineRegisterInfo & MRI,X86AddressMode & AM) X86SelectAddress() argument
546 selectLoadStoreOp(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectLoadStoreOp() argument
627 selectFrameIndexOrGep(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectFrameIndexOrGep() argument
655 selectGlobalValue(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectGlobalValue() argument
701 selectConstant(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectConstant() argument
758 selectTurnIntoCOPY(MachineInstr & I,MachineRegisterInfo & MRI,const unsigned DstReg,const TargetRegisterClass * DstRC,const unsigned SrcReg,const TargetRegisterClass * SrcRC) const selectTurnIntoCOPY() argument
773 selectTruncOrPtrToInt(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectTruncOrPtrToInt() argument
839 selectZext(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectZext() argument
904 selectAnyext(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectAnyext() argument
959 selectCmp(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectCmp() argument
1010 selectFCmp(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectFCmp() argument
1101 selectUAddSub(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectUAddSub() argument
1207 selectExtract(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectExtract() argument
1265 emitExtractSubreg(unsigned DstReg,unsigned SrcReg,MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const emitExtractSubreg() argument
1303 emitInsertSubreg(unsigned DstReg,unsigned SrcReg,MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const emitInsertSubreg() argument
1340 selectInsert(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectInsert() argument
1398 selectUnmergeValues(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) selectUnmergeValues() argument
1423 selectMergeValues(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) selectMergeValues() argument
1472 selectCondBranch(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectCondBranch() argument
1493 materializeFP(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const materializeFP() argument
1587 selectMulDivRem(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectMulDivRem() argument
1812 selectSelect(MachineInstr & I,MachineRegisterInfo & MRI,MachineFunction & MF) const selectSelect() argument
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVOptWInstrs.cpp | 121 const MachineRegisterInfo &MRI, unsigned OrigBits) { in hasAllNBitUsers() argument
345 hasAllWUsers(const MachineInstr & OrigMI,const RISCVSubtarget & ST,const MachineRegisterInfo & MRI) hasAllWUsers() argument
352 isSignExtendingOpW(const MachineInstr & MI,const MachineRegisterInfo & MRI,unsigned OpNo) isSignExtendingOpW() argument
397 isSignExtendedW(Register SrcReg,const RISCVSubtarget & ST,const MachineRegisterInfo & MRI,SmallPtrSetImpl<MachineInstr * > & FixableDef) isSignExtendedW() argument
633 removeSExtWInstrs(MachineFunction & MF,const RISCVInstrInfo & TII,const RISCVSubtarget & ST,MachineRegisterInfo & MRI) removeSExtWInstrs() argument
685 stripWSuffixes(MachineFunction & MF,const RISCVInstrInfo & TII,const RISCVSubtarget & ST,MachineRegisterInfo & MRI) stripWSuffixes() argument
712 appendWSuffixes(MachineFunction & MF,const RISCVInstrInfo & TII,const RISCVSubtarget & ST,MachineRegisterInfo & MRI) appendWSuffixes() argument
765 MachineRegisterInfo &MRI = MF.getRegInfo(); runOnMachineFunction() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenCommonISel.cpp | 249 return getSalvageOpsForTrunc(MRI, MI, Ops); in salvageDebugInfoForDbgValue() argument
210 getSalvageOpsForCopy(const MachineRegisterInfo & MRI,MachineInstr & Copy) getSalvageOpsForCopy() argument
217 getSalvageOpsForTrunc(const MachineRegisterInfo & MRI,MachineInstr & Trunc,SmallVectorImpl<uint64_t> & Ops) getSalvageOpsForTrunc() argument
236 salvageDebugInfoImpl(const MachineRegisterInfo & MRI,MachineInstr & MI,SmallVectorImpl<uint64_t> & Ops) salvageDebugInfoImpl() argument
|
| H A D | MIRVRegNamerUtils.h | 48 MachineRegisterInfo &MRI; variable
85 VRegRenamer(MachineRegisterInfo &MRI) : MRI(MRI) {} in VRegRenamer()
|
| H A D | MachineConvergenceVerifier.cpp | 41 Check(MRI.getUniqueVRegDef(Def.getReg()), in checkConvergenceTokenProduced() local
51 const MachineRegisterInfo &MRI = Context.getFunction()->getRegInfo(); findAndCheckConvergenceTokenUsed() local
|
| H A D | LivePhysRegs.cpp | 141 bool LivePhysRegs::available(const MachineRegisterInfo &MRI, in available() argument
176 const MachineRegisterInfo &MRI = MF.getRegInfo(); in addCalleeSavedRegs() local
251 const MachineRegisterInfo &MRI = MF.getRegInfo(); in computeLiveIns() local
262 const MachineRegisterInfo &MRI = MF.getRegInfo(); in addLiveIns() local
278 const MachineRegisterInfo &MRI = MF.getRegInfo(); recomputeLivenessFlags() local
[all...] |
| /llvm-project/llvm/unittests/Target/AMDGPU/ |
| H A D | DwarfRegMappings.cpp | 22 auto MRI = ST.getRegisterInfo(); in TEST() local
46 auto MRI = ST.getRegisterInfo(); TEST() local
[all...] |
| /llvm-project/llvm/include/llvm/Support/ |
| H A D | ModRef.h | 39 [[nodiscard]] inline bool isNoModRef(const ModRefInfo MRI) { in isNoModRef() argument
42 [[nodiscard]] inline bool isModOrRefSet(const ModRefInfo MRI) { in isModOrRefSet() argument
45 [[nodiscard]] inline bool isModAndRefSet(const ModRefInfo MRI) { in isModAndRefSet() argument
48 [[nodiscard]] inline bool isModSet(const ModRefInfo MRI) { in isModSet() argument
51 [[nodiscard]] inline bool isRefSet(const ModRefInfo MRI) { in isRefSet() argument
[all...] |
| /llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 128 void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, in checkADDrr()
176 void BPFMISimplifyPatchable::checkShift(MachineRegisterInfo *MRI, in checkShift()
190 void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI, in processCandidate()
225 void BPFMISimplifyPatchable::processDstReg(MachineRegisterInfo *MRI, in processDstReg()
286 void BPFMISimplifyPatchable::processInst(MachineRegisterInfo *MRI, in processInst()
306 MachineRegisterInfo *MRI = &MF->getRegInfo(); in removeLD() local
|
| /llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CSEInfo.h | 75 MachineRegisterInfo *MRI = nullptr; global() variable
171 const MachineRegisterInfo &MRI; global() variable
174 GISelInstProfileBuilder(FoldingSetNodeID & ID,const MachineRegisterInfo & MRI) GISelInstProfileBuilder() argument
|
| /llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXPeephole.cpp | 84 const auto &MRI = MF.getRegInfo(); in isCVTAToLocalCombinationCandidate() local
112 const auto &MRI = MF.getRegInfo(); in CombineCVTAToLocal() local
157 const auto &MRI = MF.getRegInfo(); in runOnMachineFunction() local
|
| /llvm-project/llvm/unittests/MC/AMDGPU/ |
| H A D | DwarfRegMappings.cpp | 69 auto MRI = TM->getMCRegisterInfo(); in TEST() local
50 auto MRI = TM->getMCRegisterInfo(); TEST() local
|
| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.cpp | 161 addDefUses(Register Reg,const MachineRegisterInfo & MRI) addDefUses() argument
176 addUseDef(Register Reg,const MachineRegisterInfo & MRI) addUseDef() argument
187 const MachineRegisterInfo &MRI = MF.getRegInfo(); skipCopiesOutgoing() local
201 const MachineRegisterInfo &MRI = MF.getRegInfo(); skipCopiesIncoming() local
214 const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo(); AmbiguousRegDefUseContainer() local
348 const MachineRegisterInfo &MRI = MF.getRegInfo(); setTypesAccordingToPhysicalRegister() local
414 const MachineRegisterInfo &MRI = MF.getRegInfo(); getInstrMapping() local
720 MachineRegisterInfo &MRI = OpdMapper.getMRI(); applyMappingImpl() local
[all...] |
| /llvm-project/llvm/unittests/Target/AArch64/ |
| H A D | AArch64InstPrinterTest.cpp | 27 const MCRegisterInfo &MRI) in AArch64InstPrinterTest() argument
38 MCRegisterInfo MRI; in AArch64InstPrinterTestPrintAlignedLabel() local
|
| /llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVISelLowering.cpp | 151 Register OpTypeReg = getTypeReg(MRI, OpReg); in validatePtrTypes() argument
185 Register OpTypeReg = getTypeReg(MRI, OpReg); in validateGroupWaitEventsPtr() argument
107 getTypeReg(MachineRegisterInfo * MRI,Register OpReg) getTypeReg() argument
114 doInsertBitcast(const SPIRVSubtarget & STI,MachineRegisterInfo * MRI,SPIRVGlobalRegistry & GR,MachineInstr & I,Register OpReg,unsigned OpIdx,SPIRVType * NewPtrType) doInsertBitcast() argument
207 validateGroupAsyncCopyPtr(const SPIRVSubtarget & STI,MachineRegisterInfo * MRI,SPIRVGlobalRegistry & GR,MachineInstr & I,unsigned OpIdx) validateGroupAsyncCopyPtr() argument
313 validateAccessChain(const SPIRVSubtarget & STI,MachineRegisterInfo * MRI,SPIRVGlobalRegistry & GR,MachineInstr & I) validateAccessChain() argument
331 MachineRegisterInfo *MRI = &MF.getRegInfo(); finalizeLowering() local
[all...] |