Lines Matching defs:MRI
77 bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
79 bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
81 bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI,
83 bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
85 bool selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI,
87 bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
89 bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
91 bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
93 bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
95 bool selectUAddSub(MachineInstr &I, MachineRegisterInfo &MRI,
97 bool selectDebugInstr(MachineInstr &I, MachineRegisterInfo &MRI) const;
98 bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
99 bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI,
101 bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI,
103 bool selectInsert(MachineInstr &I, MachineRegisterInfo &MRI,
105 bool selectExtract(MachineInstr &I, MachineRegisterInfo &MRI,
107 bool selectCondBranch(MachineInstr &I, MachineRegisterInfo &MRI,
109 bool selectTurnIntoCOPY(MachineInstr &I, MachineRegisterInfo &MRI,
114 bool materializeFP(MachineInstr &I, MachineRegisterInfo &MRI,
116 bool selectImplicitDefOrPHI(MachineInstr &I, MachineRegisterInfo &MRI) const;
117 bool selectMulDivRem(MachineInstr &I, MachineRegisterInfo &MRI,
119 bool selectSelect(MachineInstr &I, MachineRegisterInfo &MRI,
124 MachineRegisterInfo &MRI, MachineFunction &MF) const;
127 MachineRegisterInfo &MRI, MachineFunction &MF) const;
131 MachineRegisterInfo &MRI) const;
211 MachineRegisterInfo &MRI) const {
212 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI);
247 MachineRegisterInfo &MRI) const {
256 LLT Ty = MRI.getType(Reg);
257 const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
269 RBI.constrainGenericRegister(Reg, *RC, MRI);
277 MachineRegisterInfo &MRI) const {
279 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI);
280 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
283 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
284 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI);
293 getRegClass(MRI.getType(SrcReg), SrcRegBank);
298 Register ExtSrc = MRI.createVirtualRegister(DstRC);
319 DstSize <= RBI.getSizeInBits(SrcReg, MRI, TRI))) &&
323 getRegClass(MRI.getType(DstReg), DstRegBank);
341 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg);
343 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
359 MachineRegisterInfo &MRI = MF.getRegInfo();
369 return selectCopy(I, MRI);
372 return selectDebugInstr(I, MRI);
391 return selectLoadStoreOp(I, MRI, MF);
394 return selectFrameIndexOrGep(I, MRI, MF);
396 return selectGlobalValue(I, MRI, MF);
398 return selectConstant(I, MRI, MF);
400 return materializeFP(I, MRI, MF);
403 return selectTruncOrPtrToInt(I, MRI, MF);
405 return selectCopy(I, MRI);
407 return selectZext(I, MRI, MF);
409 return selectAnyext(I, MRI, MF);
411 return selectCmp(I, MRI, MF);
413 return selectFCmp(I, MRI, MF);
418 return selectUAddSub(I, MRI, MF);
420 return selectUnmergeValues(I, MRI, MF);
423 return selectMergeValues(I, MRI, MF);
425 return selectExtract(I, MRI, MF);
427 return selectInsert(I, MRI, MF);
429 return selectCondBranch(I, MRI, MF);
432 return selectImplicitDefOrPHI(I, MRI);
440 return selectMulDivRem(I, MRI, MF);
442 return selectSelect(I, MRI, MF);
534 const MachineRegisterInfo &MRI,
537 assert(MRI.getType(I.getOperand(0).getReg()).isPointer() &&
541 if (auto COff = getIConstantVRegSExtVal(I.getOperand(2).getReg(), MRI)) {
560 MachineRegisterInfo &MRI,
568 LLT Ty = MRI.getType(DefReg);
569 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
595 const MachineInstr *Ptr = MRI.getVRegDef(I.getOperand(1).getReg());
618 X86SelectAddress(*Ptr, MRI, AM);
643 MachineRegisterInfo &MRI,
651 LLT Ty = MRI.getType(DefReg);
671 MachineRegisterInfo &MRI,
704 LLT Ty = MRI.getType(DefReg);
717 MachineRegisterInfo &MRI,
723 LLT Ty = MRI.getType(DefReg);
725 if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID)
774 MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg,
778 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
779 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
789 MachineRegisterInfo &MRI,
798 const LLT DstTy = MRI.getType(DstReg);
799 const LLT SrcTy = MRI.getType(SrcReg);
801 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
802 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
820 return selectTurnIntoCOPY(I, MRI, DstReg, DstRC, SrcReg, SrcRC);
841 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
842 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
855 MachineRegisterInfo &MRI,
862 const LLT DstTy = MRI.getType(DstReg);
863 const LLT SrcTy = MRI.getType(SrcReg);
896 MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
900 DefReg = MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
920 MachineRegisterInfo &MRI,
927 const LLT DstTy = MRI.getType(DstReg);
928 const LLT SrcTy = MRI.getType(SrcReg);
930 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
931 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
946 return selectTurnIntoCOPY(I, MRI, SrcReg, SrcRC, DstReg, DstRC);
951 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
952 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
975 MachineRegisterInfo &MRI,
991 LLT Ty = MRI.getType(LHS);
1026 MachineRegisterInfo &MRI,
1053 LLT Ty = MRI.getType(LhsReg);
1068 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI);
1075 Register FlagReg1 = MRI.createVirtualRegister(&X86::GR8RegClass);
1076 Register FlagReg2 = MRI.createVirtualRegister(&X86::GR8RegClass);
1117 MachineRegisterInfo &MRI,
1134 const LLT DstTy = MRI.getType(DstReg);
1168 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
1176 MachineInstr *Def = MRI.getVRegDef(CarryInReg);
1179 Def = MRI.getVRegDef(CarryInReg);
1192 if (!RBI.constrainGenericRegister(CarryInReg, *DstRC, MRI))
1196 } else if (auto val = getIConstantVRegVal(CarryInReg, MRI)) {
1215 !RBI.constrainGenericRegister(CarryOutReg, *DstRC, MRI))
1223 MachineRegisterInfo &MRI,
1232 const LLT DstTy = MRI.getType(DstReg);
1233 const LLT SrcTy = MRI.getType(SrcReg);
1244 if (!emitExtractSubreg(DstReg, SrcReg, I, MRI, MF))
1281 MachineRegisterInfo &MRI,
1283 const LLT DstTy = MRI.getType(DstReg);
1284 const LLT SrcTy = MRI.getType(SrcReg);
1300 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
1301 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1305 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1306 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1319 MachineRegisterInfo &MRI,
1321 const LLT DstTy = MRI.getType(DstReg);
1322 const LLT SrcTy = MRI.getType(SrcReg);
1339 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1340 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
1342 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
1343 !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
1356 MachineRegisterInfo &MRI,
1365 const LLT DstTy = MRI.getType(DstReg);
1366 const LLT InsertRegTy = MRI.getType(InsertReg);
1375 if (Index == 0 && MRI.getVRegDef(SrcReg)->isImplicitDef()) {
1377 if (!emitInsertSubreg(DstReg, InsertReg, I, MRI, MF))
1414 MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) {
1421 unsigned DefSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
1439 MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) {
1448 const LLT DstTy = MRI.getType(DstReg);
1449 const LLT SrcTy = MRI.getType(SrcReg0);
1452 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1455 Register DefReg = MRI.createGenericVirtualRegister(DstTy);
1456 MRI.setRegBank(DefReg, RegBank);
1457 if (!emitInsertSubreg(DefReg, I.getOperand(1).getReg(), I, MRI, MF))
1461 Register Tmp = MRI.createGenericVirtualRegister(DstTy);
1462 MRI.setRegBank(Tmp, RegBank);
1488 MachineRegisterInfo &MRI,
1509 MachineRegisterInfo &MRI,
1520 const LLT DstTy = MRI.getType(DstReg);
1521 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI);
1539 Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass);
1577 MachineInstr &I, MachineRegisterInfo &MRI) const {
1584 if (!MRI.getRegClassOrNull(DstReg)) {
1585 const LLT DstTy = MRI.getType(DstReg);
1586 const TargetRegisterClass *RC = getRegClass(DstTy, DstReg, MRI);
1588 if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
1604 MachineRegisterInfo &MRI,
1620 const LLT RegTy = MRI.getType(DstReg);
1621 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) &&
1624 const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);
1746 if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) ||
1747 !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) ||
1748 !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {
1765 Register Zero32 = MRI.createVirtualRegister(&X86::GR32RegClass);
1803 Register SourceSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
1804 Register ResultSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
1829 MachineRegisterInfo &MRI,
1838 LLT Ty = MRI.getType(DstReg);
1861 const TargetRegisterClass *DstRC = getRegClass(Ty, DstReg, MRI);
1862 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {