/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMInstPrinter.cpp | 398 MO1.getExpr()->print(O, &MAI); in printThumbLdrLabelOperand() local 130 const MCOperand &MO1 = MI->getOperand(1); printInst() local 153 const MCOperand &MO1 = MI->getOperand(1); printInst() local 429 const MCOperand &MO1 = MI->getOperand(OpNum); printSORegRegOperand() local 449 const MCOperand &MO1 = MI->getOperand(OpNum); printSORegImmOperand() local 466 const MCOperand &MO1 = MI->getOperand(Op); printAM2PreOrOffsetIndexOp() local 497 const MCOperand &MO1 = MI->getOperand(Op); printAddrModeTBB() local 511 const MCOperand &MO1 = MI->getOperand(Op); printAddrModeTBH() local 526 const MCOperand &MO1 = MI->getOperand(Op); printAddrMode2Operand() local 546 const MCOperand &MO1 = MI->getOperand(OpNum); printAddrMode2OffsetOperand() local 571 const MCOperand &MO1 = MI->getOperand(Op); printAM3PreOrOffsetIndexOp() local 601 const MCOperand &MO1 = MI->getOperand(Op); printAddrMode3Operand() local 617 const MCOperand &MO1 = MI->getOperand(OpNum); printAddrMode3OffsetOperand() local 644 const MCOperand &MO1 = MI->getOperand(OpNum); printPostIdxRegOperand() local 664 const MCOperand &MO1 = MI->getOperand(OpNum); printMveAddrModeRQOperand() local 691 const MCOperand &MO1 = MI->getOperand(OpNum); printAddrMode5Operand() local 717 const MCOperand &MO1 = MI->getOperand(OpNum); printAddrMode5FP16Operand() local 743 const MCOperand &MO1 = MI->getOperand(OpNum); printAddrMode6Operand() local 758 const MCOperand &MO1 = MI->getOperand(OpNum); printAddrMode7Operand() local 1133 const MCOperand &MO1 = MI->getOperand(Op); printThumbAddrModeRROperand() local 1156 const MCOperand &MO1 = MI->getOperand(Op); printThumbAddrModeImm5SOperand() local 1208 const MCOperand &MO1 = MI->getOperand(OpNum); printT2SOOperand() local 1224 const MCOperand &MO1 = MI->getOperand(OpNum); printAddrModeImm12Operand() local 1256 const MCOperand &MO1 = MI->getOperand(OpNum); printT2AddrModeImm8Operand() local 1283 const MCOperand &MO1 = MI->getOperand(OpNum); printT2AddrModeImm8s4Operand() local 1316 const MCOperand &MO1 = MI->getOperand(OpNum); printT2AddrModeImm0_1020s4Operand() local 1332 const MCOperand &MO1 = MI->getOperand(OpNum); printT2AddrModeImm8OffsetOperand() local 1347 const MCOperand &MO1 = MI->getOperand(OpNum); printT2AddrModeImm8s4OffsetOperand() local 1366 const MCOperand &MO1 = MI->getOperand(OpNum); printT2AddrModeSoRegOperand() local [all...] |
H A D | ARMMCTargetDesc.cpp | 446 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); evaluateMemOpAddrForAddrMode_i12() local 464 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); evaluateMemOpAddrForAddrMode3() local 484 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); evaluateMemOpAddrForAddrMode5() local 503 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); evaluateMemOpAddrForAddrMode5FP16() local 523 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); evaluateMemOpAddrForAddrModeT2_i8s4() local 541 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); evaluateMemOpAddrForAddrModeT2_pc() local [all...] |
H A D | ARMMCCodeEmitter.cpp | 920 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue() local 1176 unsigned Imm8 = MO1 in getT2AddrModeImm0_1020s4OpValue() local 585 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); EncodeAddrModeOpValues() local 975 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getAddrModeImm12OpValue() local 1274 const MCOperand &MO1 = MI.getOperand(OpIdx+1); getLdStSORegOpValue() local 1311 const MCOperand &MO1 = MI.getOperand(OpIdx+1); getAddrMode2OffsetOpValue() local 1333 const MCOperand &MO1 = MI.getOperand(OpIdx+1); getPostIdxRegOpValue() local 1347 const MCOperand &MO1 = MI.getOperand(OpIdx+1); getAddrMode3OffsetOpValue() local 1368 const MCOperand &MO1 = MI.getOperand(OpIdx+1); getAddrMode3OpValue() local 1401 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getAddrModeThumbSPOpValue() local 1419 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getAddrModeISOpValue() local 1531 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getSORegRegOpValue() local 1577 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getSORegImmOpValue() local 1615 const MCOperand &MO1 = MI.getOperand(OpNum); getT2AddrModeSORegOpValue() local 1635 const MCOperand &MO1 = MI.getOperand(OpNum); getT2AddrModeImmOpValue() local 1660 const MCOperand &MO1 = MI.getOperand(OpNum); getT2AddrModeImm8OffsetOpValue() local 1686 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getT2SORegOpValue() local [all...] |
/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/ |
H A D | MSP430MCCodeEmitter.cpp | 125 unsigned Reg = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getMemOpValue() local
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/llvm-project/llvm/lib/Target/X86/ |
H A D | X86OptimizeLEAs.cpp | 201 static inline bool isIdenticalOp(const MachineOperand &MO1, in isIdenticalOp() argument 213 static bool isSimilarDispOp(const MachineOperand &MO1, in isSimilarDispOp() argument [all...] |
H A D | X86RegisterInfo.cpp | 1065 MachineOperand &MO1 = MI->getOperand(1); getTileShape() local
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H A D | X86FloatingPoint.cpp | 1527 const MachineOperand &MO1 = MI.getOperand(1); handleSpecialFP() local
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H A D | X86InstrInfo.cpp | 8454 MachineOperand &MO1 = DataMI->getOperand(1); unfoldMemoryOperand() local
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/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 202 auto BasePseudoVal1 = MO1->getPseudoValue(); in getHazardType() local
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H A D | ARMAsmPrinter.cpp | 995 const MachineOperand &MO1 = MI->getOperand(1); emitJumpTableAddrs() local 1041 const MachineOperand &MO1 = MI->getOperand(1); emitJumpTableInsts() local 1071 const MachineOperand &MO1 = MI->getOperand(1); emitJumpTableTBInst() local
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H A D | ARMExpandPseudoInsts.cpp | 2645 const MachineOperand &MO1 = MI.getOperand(1); ExpandMI() local 2706 const MachineOperand &MO1 = MI.getOperand(1); ExpandMI() local
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H A D | ARMBaseInstrInfo.cpp | 1877 const MachineOperand &MO1 = MI1.getOperand(1); produceSameValue() local 1930 const MachineOperand &MO1 = MI1.getOperand(i); produceSameValue() local
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/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVInstPrinter.cpp | 270 const MCOperand &MO1 = MI->getOperand(OpNo + 1); printRegReg() local
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H A D | RISCVMCCodeEmitter.cpp | 561 const MCOperand &MO1 = MI.getOperand(OpNo + 1); getRegReg() local
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/llvm-project/llvm/unittests/CodeGen/ |
H A D | MachineOperandTest.cpp | 420 MachineOperand MO1 = MachineOperand::CreateES(SymName1); in TEST() local
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/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 465 MCOperand &MO1 = MappedInst.getOperand(1); HexagonProcessInstruction() local
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/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 1288 makeCombineInst(int opCode,MCOperand & Rdd,MCOperand & MO1,MCOperand & MO2) makeCombineInst() argument 1650 MCOperand &MO1 = Inst.getOperand(1); processInstruction() local 1665 MCOperand &MO1 = Inst.getOperand(1); processInstruction() local
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/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchExpandPseudoInsts.cpp | 509 unsigned MO0, MO1, MO2, MO3; expandLargeAddressLoad() local
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/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCCodeEmitter.cpp | 286 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); getAddSubImmOpValue() local
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H A D | AArch64InstPrinter.cpp | 1427 const MCOperand MO1 = MI->getOperand(OpNum + 1); printAMIndexedWB() local
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/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandPseudoInsts.cpp | 1298 const MachineOperand &MO1 = MI.getOperand(1); expandMI() local [all...] |
/llvm-project/llvm/lib/CodeGen/ |
H A D | RegAllocFast.cpp | 1338 const MachineOperand &MO1 = MI.getOperand(I1); findAndSortDefOperandIndexes() local
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H A D | MachineVerifier.cpp | 3151 const MachineOperand &MO1 = Phi.getOperand(I + 1); checkPHIOps() local
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/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfo.cpp | 2660 auto MO1 = *MI1.memoperands_begin(); memOpsHaveSameBasePtr() local
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/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 532 auto MO1 = *MI1.memoperands_begin(); memOpsHaveSameBasePtr() local
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