| /llvm-project/llvm/unittests/Target/RISCV/ |
| H A D | RISCVInstrInfoTest.cpp | 84 MachineInstr *MI2 = in TEST_P() local
111 MachineInstr *MI2 = BuildMI(*MF, DL, TII->get(RISCV::ADDI), RISCV::X1) in TEST_P() local
271 auto *MI2 = BuildMI(*MBB, MBB->begin(), DL, TII->get(RISCV::ADDI), RISCV::X3) TEST_P() local
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| /llvm-project/llvm/unittests/CodeGen/ |
| H A D | MachineBasicBlockTest.cpp | 75 MBB.insert(MBB.begin(), MI2); in TEST() local
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| H A D | MachineInstrTest.cpp | 73 auto MI2 = MF->CreateMachineInstr(Table.MCID, DebugLoc()); in TEST() local
107 void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) { in checkHashAndIsEqualMatch() argument
[all...] |
| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsSizeReduction.cpp | 398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr()
465 MachineInstr *MI2 = &*NextMII; in ReduceXWtoXWP() local
622 MachineInstr *MI2 = &*NextMII; in ReduceMoveToMovep() local
695 MachineInstr *MI2, in ReplaceInstruction()
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 273 const MachineInstr &MI2, in alias()
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| H A D | TargetInstrInfo.cpp | 842 MachineInstr *MI2 = nullptr; hasReassociableOperands() local
862 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); hasReassociableSibling() local
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| /llvm-project/lldb/test/Shell/SymbolFile/NativePDB/ |
| H A D | ast-types.cpp | 93 class MI2 : MI { int mi2; }; class
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86OptimizeLEAs.cpp | 399 const MachineInstr &MI2, in getAddrDispShift() argument
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| /llvm-project/clang/test/Analysis/ |
| H A D | padding_cpp.cpp | 102 class MI2 : public PaddedA, public InnerPaddedB { // xxxexpected-warning{{Excessive padding in 'cla… class
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 1826 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(3).getReg()); hasReassociableVectorSibling() local
1855 MachineInstr *MI2 = nullptr; hasReassociableOperands() local
2649 memOpsHaveSameBasePtr(const MachineInstr & MI1,ArrayRef<const MachineOperand * > BaseOps1,const MachineInstr & MI2,ArrayRef<const MachineOperand * > BaseOps2) memOpsHaveSameBasePtr() argument
3863 hasEqualFRM(const MachineInstr & MI1,const MachineInstr & MI2) hasEqualFRM() argument
[all...] |
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 273 if (!QII->isHVXVec(MI2)) in apply() local
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| H A D | HexagonVLIWPacketizer.cpp | 968 MachineInstr &MI2) { in arePredicatesComplements() argument
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| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.cpp | 105 aliasIsKnownForLoadStore(const MachineInstr & MI1,const MachineInstr & MI2,bool & IsAlias,MachineRegisterInfo & MRI) aliasIsKnownForLoadStore() argument
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| /llvm-project/clang-tools-extra/test/clang-tidy/checkers/bugprone/ |
| H A D | easily-swappable-parameters-len2.cpp | 148 void typedefChain(int I, MyInt1 MI1, MyInt2 MI2, MyInt2b MI2b) {} in typedefChain()
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 475 MachineInstr *MI2 = *I2; hoistAndMergeSGPRInits() local
[all...] |
| H A D | SIInstrInfo.cpp | 521 memOpsHaveSameBasePtr(const MachineInstr & MI1,ArrayRef<const MachineOperand * > BaseOps1,const MachineInstr & MI2,ArrayRef<const MachineOperand * > BaseOps2) memOpsHaveSameBasePtr() argument
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| /llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRExpandPseudoInsts.cpp | 1655 auto MI2 = in expandLSLW4Rd() local
1853 auto MI2 = in expandLSRW4Rd() local
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| /llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | AsmPrinter.cpp | 1766 auto MI2 = std::next(MI.getIterator()); emitFunctionBody() local
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