| /llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 305 splitReg(Register Reg,Register & LoReg,Register & HiReg) const splitReg() argument
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 757 Register LoReg = LoOperand.getReg(); in emitCombineIR() local
856 Register LoReg = LoOperand.getReg(); in emitCombineRR() local
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| H A D | HexagonFrameLowering.cpp | 1130 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo); insertCFIInstructionsAt() local
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| /llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcAsmPrinter.cpp | 445 Register HiReg, LoReg; PrintAsmOperand() local
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| H A D | SparcISelLowering.cpp | 1323 Register LoReg = VA.getLocReg() + 1; LowerCall_64() local
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| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 798 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| H A D | MipsSEFrameLowering.cpp | 308 Register LoReg = I->getOperand(1).getReg(); expandBuildPairF64() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 2062 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { CMSEPushCalleeSaves() local
2082 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; CMSEPushCalleeSaves() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 2245 Register LoReg = MRI->createVirtualRegister(DstRC); selectG_TRUNC() local
2594 Register LoReg = MRI->createVirtualRegister(RC); selectG_CONSTANT() local
2649 Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); selectG_FNEG() local
2687 Register LoReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); selectG_FABS() local
2971 Register LoReg = MRI->createVirtualRegister(&RegRC); selectG_PTRMASK() local
[all...] |
| H A D | SILoadStoreOptimizer.cpp | 187 Register LoReg; global() member
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5542 unsigned LoReg, ROpc, MOpc; Select() local
5621 unsigned LoReg, HiReg; Select() local
5764 unsigned LoReg, HiReg, ClrReg; Select() local
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 18073 Register LoReg = MI.getOperand(0).getReg(); emitReadCounterWidePseudo() local
18112 Register LoReg = MI.getOperand(0).getReg(); emitSplitF64Pseudo() local
18149 Register LoReg = MI.getOperand(1).getReg(); emitBuildPairF64Pseudo() local
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 13042 Register LoReg = MI.getOperand(0).getReg(); EmitInstrWithCustomInserter() local
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