/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsNaClELFStreamer.cpp | 211 if (IsStore) in isBasePlusOffsetMemoryAccess() argument 158 bool IsStore = false; emitInstruction() local [all...] |
/llvm-project/bolt/include/bolt/Passes/ |
H A D | FrameAnalysis.h | 26 bool IsStore; member
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/llvm-project/llvm/tools/llvm-reduce/deltas/ |
H A D | ReduceOpcodes.cpp | 78 const bool IsStore = CB->getType()->isVoidTy(); in callLooksLikeLoadStore() local
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/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCOptAddrMode.cpp | 405 bool IsStore = Ldst->mayStore(); in canHoistLoadStoreTo() local 454 bool IsStore = Ldst.mayStore(); in changeToAddrMode() local
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/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kCollapseMOVEMPass.cpp | 205 bool IsStore = false) { in ProcessMI()
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/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86EncodingOptimization.cpp | 362 bool IsStore = MI.getOperand(0).isReg() && MI.getOperand(1).isReg(); in optimizeMOV() local
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/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIRegisterInfo.cpp | 1226 bool IsStore = MI->mayStore(); spillVGPRtoAGPR() local 1263 bool IsStore = MI->mayStore(); buildMUBUFOffsetLoadStore() local 1295 bool IsStore = TII->get(LoadStoreOp).mayStore(); getFlatScratchSpillOpcode() local 1342 bool IsStore = Desc->mayStore(); buildSpillLoadStore() local [all...] |
H A D | AMDGPULegalizerInfo.cpp | 1426 const bool IsStore = Op == G_STORE; AMDGPULegalizerInfo() local
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/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXSwapRemoval.cpp | 75 unsigned int IsStore : 1; global() member [all...] |
/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
H A D | PPCInstructionSelector.cpp | 156 const bool IsStore = GenericOpc == TargetOpcode::G_STORE; in selectLoadStoreOp() local
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/llvm-project/clang/lib/Sema/ |
H A D | SemaRISCV.cpp | 1312 bool IsStore = BuiltinID == RISCV::BI__builtin_riscv_ntl_store; CheckBuiltinFunctionCall() local
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/llvm-project/bolt/lib/Passes/ |
H A D | ShrinkWrapping.cpp | 664 bool IsStore = false; in performChanges() local 1535 bool IsStore = false; in insertUpdatedCFI() local
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/llvm-project/llvm/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 464 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore() local
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H A D | ARMLoadStoreOptimizer.cpp | 502 bool IsStore = UpdateBaseRegUses() local
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/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandCondsets.cpp | 846 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); canMoveMemTo() local
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H A D | HexagonConstExtenders.cpp | 1148 bool IsStore = MI.mayStore(); in recordExtender() local
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/llvm-project/clang/lib/CodeGen/ |
H A D | CGAtomic.cpp | 1225 bool IsStore = E->getOp() == AtomicExpr::AO__c11_atomic_store || EmitAtomicExpr() local
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/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUInstPrinter.cpp | 217 bool IsStore = TID.mayStore(); printTH() local
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/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 5063 bool IsStore = (Instruction::Store == Opcode); getMaskedMemoryOpCost() local
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/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
H A D | AMDGPUBaseInfo.cpp | 1475 getCombinedCountBitMask(const IsaVersion & Version,bool IsStore) getCombinedCountBitMask() argument
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/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 2966 bool IsStore = isa<GStore>(I); select() local
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/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 4998 bool IsStore = TID.mayStore(); validateTHAndScopeBits() local
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/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | CombinerHelper.cpp | 1446 bool IsStore = Opcode == TargetOpcode::G_STORE; applyCombineIndexedLoadStore() local
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/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 1574 __anon17a3f42a0502(unsigned PtrOp, bool IsStore, bool IsUnitStrided, bool UsePtrVal = false) getTgtMemIntrinsic() argument [all...] |
/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 23000 bool IsStore = false; performNEONPostLDSTCombine() local [all...] |