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Searched defs:IsStore (Results 1 – 25 of 25) sorted by relevance

/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp211 if (IsStore) in isBasePlusOffsetMemoryAccess() argument
158 bool IsStore = false; emitInstruction() local
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/llvm-project/bolt/include/bolt/Passes/
H A DFrameAnalysis.h26 bool IsStore; member
/llvm-project/llvm/tools/llvm-reduce/deltas/
H A DReduceOpcodes.cpp78 const bool IsStore = CB->getType()->isVoidTy(); in callLooksLikeLoadStore() local
/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp405 bool IsStore = Ldst->mayStore(); in canHoistLoadStoreTo() local
454 bool IsStore = Ldst.mayStore(); in changeToAddrMode() local
/llvm-project/llvm/lib/Target/M68k/
H A DM68kCollapseMOVEMPass.cpp205 bool IsStore = false) { in ProcessMI()
/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86EncodingOptimization.cpp362 bool IsStore = MI.getOperand(0).isReg() && MI.getOperand(1).isReg(); in optimizeMOV() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp1226 bool IsStore = MI->mayStore(); spillVGPRtoAGPR() local
1263 bool IsStore = MI->mayStore(); buildMUBUFOffsetLoadStore() local
1295 bool IsStore = TII->get(LoadStoreOp).mayStore(); getFlatScratchSpillOpcode() local
1342 bool IsStore = Desc->mayStore(); buildSpillLoadStore() local
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H A DAMDGPULegalizerInfo.cpp1426 const bool IsStore = Op == G_STORE; AMDGPULegalizerInfo() local
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp75 unsigned int IsStore : 1; global() member
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/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp156 const bool IsStore = GenericOpc == TargetOpcode::G_STORE; in selectLoadStoreOp() local
/llvm-project/clang/lib/Sema/
H A DSemaRISCV.cpp1312 bool IsStore = BuiltinID == RISCV::BI__builtin_riscv_ntl_store; CheckBuiltinFunctionCall() local
/llvm-project/bolt/lib/Passes/
H A DShrinkWrapping.cpp664 bool IsStore = false; in performChanges() local
1535 bool IsStore = false; in insertUpdatedCFI() local
/llvm-project/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp464 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore() local
H A DARMLoadStoreOptimizer.cpp502 bool IsStore = UpdateBaseRegUses() local
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp846 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); canMoveMemTo() local
H A DHexagonConstExtenders.cpp1148 bool IsStore = MI.mayStore(); in recordExtender() local
/llvm-project/clang/lib/CodeGen/
H A DCGAtomic.cpp1225 bool IsStore = E->getOp() == AtomicExpr::AO__c11_atomic_store || EmitAtomicExpr() local
/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp217 bool IsStore = TID.mayStore(); printTH() local
/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp5063 bool IsStore = (Instruction::Store == Opcode); getMaskedMemoryOpCost() local
/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp1475 getCombinedCountBitMask(const IsaVersion & Version,bool IsStore) getCombinedCountBitMask() argument
/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp2966 bool IsStore = isa<GStore>(I); select() local
/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4998 bool IsStore = TID.mayStore(); validateTHAndScopeBits() local
/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1446 bool IsStore = Opcode == TargetOpcode::G_STORE; applyCombineIndexedLoadStore() local
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1574 __anon17a3f42a0502(unsigned PtrOp, bool IsStore, bool IsUnitStrided, bool UsePtrVal = false) getTgtMemIntrinsic() argument
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/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp23000 bool IsStore = false; performNEONPostLDSTCombine() local
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