| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 158 bool IsStore = false; in emitInstruction() local
211 bool *IsStore) { in isBasePlusOffsetMemoryAccess() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 405 bool IsStore = Ldst->mayStore(); in canHoistLoadStoreTo() local
454 bool IsStore = Ldst.mayStore(); in changeToAddrMode() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kCollapseMOVEMPass.cpp | 205 bool IsStore = false) { in ProcessMI()
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86EncodingOptimization.cpp | 339 bool IsStore = MI.getOperand(0).isReg() && MI.getOperand(1).isReg(); optimizeMOV() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1217 bool IsStore = MI->mayStore(); spillVGPRtoAGPR() local
1254 bool IsStore = MI->mayStore(); buildMUBUFOffsetLoadStore() local
1286 bool IsStore = TII->get(LoadStoreOp).mayStore(); getFlatScratchSpillOpcode() local
1333 bool IsStore = Desc->mayStore(); buildSpillLoadStore() local
[all...] |
| H A D | AMDGPULegalizerInfo.cpp | 1379 const bool IsStore = Op == G_STORE; AMDGPULegalizerInfo() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXSwapRemoval.cpp | 75 unsigned int IsStore : 1; member
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 156 const bool IsStore = GenericOpc == TargetOpcode::G_STORE; in selectLoadStoreOp() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 464 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore() local
|
| H A D | ARMLoadStoreOptimizer.cpp | 502 bool IsStore = in UpdateBaseRegUses() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 845 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); canMoveMemTo() local
|
| H A D | HexagonConstExtenders.cpp | 1148 bool IsStore = MI.mayStore(); in recordExtender() local
|
| /freebsd-src/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGAtomic.cpp | 1449 bool IsStore = E->getOp() == AtomicExpr::AO__c11_atomic_store || EmitAtomicExpr() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 212 bool IsStore = TID.mayStore(); printTH() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 4937 bool IsStore = (Instruction::Store == Opcode); getMaskedMemoryOpCost() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 1374 getCombinedCountBitMask(const IsaVersion & Version,bool IsStore) getCombinedCountBitMask() argument
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2981 bool IsStore = isa<GStore>(I); in select() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1284 bool IsStore = Opcode == TargetOpcode::G_STORE; applyCombineIndexedLoadStore() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 4828 bool IsStore = TID.mayStore(); validateTHAndScopeBits() local
|
| /freebsd-src/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaChecking.cpp | 6057 bool IsStore = BuiltinID == RISCV::BI__builtin_riscv_ntl_store; CheckRISCVBuiltinFunctionCall() local
|
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1467 __anonbba6e2090502(unsigned PtrOp, bool IsStore, bool IsUnitStrided) getTgtMemIntrinsic() argument
[all...] |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 21780 bool IsStore = false; performNEONPostLDSTCombine() local
[all...] |