| /llvm-project/llvm/unittests/DebugInfo/DWARF/ |
| H A D | DWARFDebugFrameTest.cpp | 781 dwarf::DW_CFA_register, Reg, InReg}), in TEST() local
869 constexpr uint8_t InReg = 14; TEST() local
932 constexpr uint8_t InReg = 14; TEST() local
1355 constexpr uint8_t InReg = 14; TEST() local
1503 constexpr uint8_t InReg = 14; TEST() local
1599 constexpr uint8_t InReg = 14; TEST() local
[all...] |
| /llvm-project/clang/lib/CodeGen/Targets/ |
| H A D | Lanai.cpp | 126 bool InReg = shouldUseInReg(Ty, State); in classifyArgumentType() local
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| H A D | Sparc.cpp | 133 bool InReg; member
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| H A D | X86.cpp | 676 shouldAggregateUseDirect(QualType Ty,CCState & State,bool & InReg,bool & NeedsPadding) const shouldAggregateUseDirect() argument
814 bool InReg; classifyArgumentType() local
889 bool InReg = shouldPrimitiveUseInReg(Ty, State); classifyArgumentType() local
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCTLSDynamicCall.cpp | 95 Register InReg = PPC::NoRegister; processBlock() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64Arm64ECCallLowering.cpp | 409 auto InReg = Attrs.getParamAttr(0, Attribute::InReg); buildExitThunk() local
[all...] |
| /llvm-project/clang/include/clang/CodeGen/ |
| H A D | CGFunctionInfo.h | 116 bool InReg : 1; // isDirect() || isExtend() || isIndirect() variable
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | StatepointLowering.cpp | 1241 Register InReg = Record.payload.Reg; in visitGCRelocate() local
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| H A D | SelectionDAGBuilder.cpp | 1735 Register InReg = It->second; getCopyFromRegs() local
1945 Register InReg = FuncInfo.InitializeRegForValue(Inst); getValueImpl() local
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 633 const bool InReg = Arg.hasAttribute(Attribute::InReg); lowerFormalArguments() local
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| H A D | AMDGPUMachineCFGStructurizer.cpp | |
| H A D | AMDGPUInstructionSelector.cpp | 2352 bool InReg = I.getOpcode() == AMDGPU::G_SEXT_INREG; selectG_SZA_EXT() local
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| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 468 Register InReg = MI.getOperand(1).getReg(); LowerFPToInt() local
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 853 bool InReg = VA.isRegLoc() && LowerFormalArguments() local
|