| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 806 Register HiReg = HiOperand.getReg(); in emitCombineRI() local
857 Register HiReg = HiOperand.getReg(); in emitCombineRR() local
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| H A D | HexagonFrameLowering.cpp | 1129 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); insertCFIInstructionsAt() local
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| /llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcAsmPrinter.cpp | 445 Register HiReg, LoReg; PrintAsmOperand() local
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| H A D | SparcISelLowering.cpp | 1322 Register HiReg = VA.getLocReg(); LowerCall_64() local
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| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 798 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| H A D | MipsSEFrameLowering.cpp | 309 Register HiReg = I->getOperand(2).getReg(); expandBuildPairF64() local
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| H A D | MipsISelLowering.cpp | 2989 MCRegister HiReg = State.AllocateReg(IntRegs); CC_MipsO32() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1427 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); selectBallot() local
2246 Register HiReg = MRI->createVirtualRegister(DstRC); selectG_TRUNC() local
2436 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); selectG_SZA_EXT() local
2595 Register HiReg = MRI->createVirtualRegister(RC); selectG_CONSTANT() local
2650 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); selectG_FNEG() local
2688 Register HiReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); selectG_FABS() local
2970 Register HiReg = MRI->createVirtualRegister(&RegRC); selectG_PTRMASK() local
[all...] |
| H A D | SILoadStoreOptimizer.cpp | 188 Register HiReg; global() member
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 2062 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { CMSEPushCalleeSaves() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5621 unsigned LoReg, HiReg; Select() local
5764 unsigned LoReg, HiReg, ClrReg; Select() local
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 18074 Register HiReg = MI.getOperand(1).getReg(); emitReadCounterWidePseudo() local
18113 Register HiReg = MI.getOperand(1).getReg(); emitSplitF64Pseudo() local
18150 Register HiReg = MI.getOperand(2).getReg(); emitBuildPairF64Pseudo() local
19043 Register HiReg = State.AllocateReg(ArgGPRs); CC_RISCV() local
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| /llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 7463 checkLowRegisterList(const MCInst & Inst,unsigned OpNo,unsigned Reg,unsigned HiReg,bool & containsReg) checkLowRegisterList() argument
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 13043 Register HiReg = MI.getOperand(1).getReg(); EmitInstrWithCustomInserter() local
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