| /llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 1682 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) printVectorList() local
1684 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) printVectorList() local
1686 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) printVectorList() local
1688 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::psub0)) printVectorList() local
|
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 386 Register FirstReg; CreateRegs() local
|
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 491 unsigned FirstReg = 0; ScanInstruction() local
|
| /llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3435 unsigned FirstReg = Inst.getOperand(0).getReg(); expandLoadSingleImmToGPR() local
3452 unsigned FirstReg = Inst.getOperand(0).getReg(); expandLoadSingleImmToFPR() local
3506 unsigned FirstReg = Inst.getOperand(0).getReg(); expandLoadDoubleImmToGPR() local
3571 unsigned FirstReg = Inst.getOperand(0).getReg(); expandLoadDoubleImmToFPR() local
4412 unsigned FirstReg = Inst.getOperand(0).getReg(); expandTrunc() local
5354 unsigned FirstReg = Inst.getOperand(0).getReg(); expandLoadStoreDMacro() local
5401 unsigned FirstReg = Inst.getOperand(0).getReg(); expandStoreDM1Macro() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 2257 CanFormLdStDWord(MachineInstr * Op0,MachineInstr * Op1,DebugLoc & dl,unsigned & NewOpc,Register & FirstReg,Register & SecondReg,Register & BaseReg,int & Offset,Register & PredReg,ARMCC::CondCodes & Pred,bool & isT2) CanFormLdStDWord() argument
2416 Register FirstReg, SecondReg; RescheduleOps() local
[all...] |
| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 4378 copyByValRegs(SDValue Chain,const SDLoc & DL,std::vector<SDValue> & OutChains,SelectionDAG & DAG,const ISD::ArgFlagsTy & Flags,SmallVectorImpl<SDValue> & InVals,const Argument * FuncArg,unsigned FirstReg,unsigned LastReg,const CCValAssign & VA,MipsCCState & State) const copyByValRegs() argument
4431 passByValArg(SDValue Chain,const SDLoc & DL,std::deque<std::pair<unsigned,SDValue>> & RegsToPass,SmallVectorImpl<SDValue> & MemOpChains,SDValue StackPtr,MachineFrameInfo & MFI,SelectionDAG & DAG,SDValue Arg,unsigned FirstReg,unsigned LastReg,const ISD::ArgFlagsTy & Flags,bool isLittle,const CCValAssign & VA) const passByValArg() argument
4578 unsigned FirstReg = 0; HandleByVal() local
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1862 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; addVectorListOperands() local
4416 unsigned FirstReg, ElementWidth; tryParseMatrixTileList() local
4506 MCRegister FirstReg; tryParseVectorList() local
7878 MCRegister FirstReg; tryParseGPRSeqPair() local
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 2896 unsigned FirstReg = 0; computeCalleeSaveRegisterPairs() local
|
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1629 Register FirstReg = SwapOps ? FalseReg : TrueReg, insertSelect() local
|
| H A D | PPCISelLowering.cpp | 7063 const unsigned FirstReg = State.AllocateReg(PPC::R9); CC_AIX() local
|
| /llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 4897 unsigned FirstReg = Reg; parseVectorList() local
|