MipsAsmParser.cpp - OpenGrok cross reference for /llvm-project/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Lines Matching defs:FirstReg
3438   unsigned FirstReg = Inst.getOperand(0).getReg();
3443   return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc,
3455   unsigned FirstReg = Inst.getOperand(0).getReg();
3473     TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);
3496   TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr),
3509   unsigned FirstReg = Inst.getOperand(0).getReg();
3516       if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false,
3520       if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false,
3524       if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false,
3558     TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI);
3560     TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI);
3561     TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI);
3574   unsigned FirstReg = Inst.getOperand(0).getReg();
3593       TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);
3603       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
3604       TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI);
3606       TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI);
3607       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
3633   TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, TmpReg,
4415   unsigned FirstReg = Inst.getOperand(0).getReg();
4432                 FirstReg, SecondReg, IDLoc, STI);
4440               FirstReg, SecondReg, IDLoc, STI);
5357   unsigned FirstReg = Inst.getOperand(0).getReg();
5358   unsigned SecondReg = nextReg(FirstReg);
5363   warnIfRegIndexIsAT(FirstReg, IDLoc);
5376   // first if the BaseReg == FirstReg.
5377   if (FirstReg != BaseReg || !IsLoad) {
5378     TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
5382     TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
5404   unsigned FirstReg = Inst.getOperand(0).getReg();
5405   unsigned SecondReg = nextReg(FirstReg);
5410   warnIfRegIndexIsAT(FirstReg, IDLoc);
5423     std::swap(FirstReg, SecondReg);
5425   TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);