| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVFoldMasks.cpp | |
| H A D | RISCVInstrInfo.cpp | 1415 MachineOperand FalseReg = MI.getOperand(Invert ? 5 : 4); optimizeSelect() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CmovConversion.cpp | 732 Register FalseReg = in convertCmovInstsToBranches() local
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| H A D | X86InstrInfo.cpp | 4100 canInsertSelect(const MachineBasicBlock & MBB,ArrayRef<MachineOperand> Cond,Register DstReg,Register TrueReg,Register FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) const canInsertSelect() argument
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| /llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 505 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 936 canInsertSelect(const MachineBasicBlock & MBB,ArrayRef<MachineOperand> Cond,Register DstReg,Register TrueReg,Register FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) canInsertSelect() argument
960 insertSelect(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,Register DstReg,ArrayRef<MachineOperand> Cond,Register TrueReg,Register FalseReg) insertSelect() argument
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| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 925 Register FalseReg = getRegForValue(Select->getFalseValue()); selectSelect() local
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| H A D | WebAssemblyISelLowering.cpp | 503 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; LowerFPToInt() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 790 auto FalseReg = MIB.getReg(3); in selectSelect() local
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| H A D | ARMBaseInstrInfo.cpp | 2355 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1); optimizeSelect() local
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1523 canInsertSelect(const MachineBasicBlock & MBB,ArrayRef<MachineOperand> Cond,Register DstReg,Register TrueReg,Register FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) const canInsertSelect() argument
3254 selectReg(int64_t Imm1,int64_t Imm2,unsigned CompareOpc,unsigned TrueReg,unsigned FalseReg,unsigned CRSubReg) selectReg() argument
4608 Register FalseReg = CompareUseMI.getOperand(2).getReg(); simplifyToLI() local
[all...] |
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 553 canInsertSelect(const MachineBasicBlock & MBB,ArrayRef<MachineOperand> Pred,Register DstReg,Register TrueReg,Register FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) const canInsertSelect() argument
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| H A D | SystemZISelLowering.cpp | 8261 Register FalseReg = MI->getOperand(2).getReg(); createPHIsForSelects() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 705 canInsertSelect(const MachineBasicBlock & MBB,ArrayRef<MachineOperand> Cond,Register DstReg,Register TrueReg,Register FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) const canInsertSelect() argument
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 3225 canInsertSelect(const MachineBasicBlock & MBB,ArrayRef<MachineOperand> Cond,Register DstReg,Register TrueReg,Register FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) const canInsertSelect() argument
[all...] |