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Searched defs:ExtTy (Results 1 – 24 of 24) sorted by relevance

/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.h136 shouldReduceLoadWidth(SDNode * Load,ISD::LoadExtType ExtTy,EVT NewVT) shouldReduceLoadWidth() argument
/llvm-project/llvm/unittests/IR/
H A DVectorTypesTest.cpp96 auto *ExtTy = dyn_cast<FixedVectorType>( in TEST() local
191 auto *ExtTy = dyn_cast<ScalableVectorType>( TEST() local
/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h2174 Type *ExtTy = RetTy->getWithNewBitWidth(ExtSize); getTypeBasedIntrinsicInstrCost() local
2240 Type *ExtTy = MulTy->getWithNewBitWidth(ExtSize); getTypeBasedIntrinsicInstrCost() local
2602 VectorType *ExtTy = VectorType::get(ResTy, Ty); getExtendedReductionCost() local
2618 VectorType *ExtTy = VectorType::get(ResTy, Ty); getMulAccReductionCost() local
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H A DTargetLowering.h1797 shouldReduceLoadWidth(SDNode * Load,ISD::LoadExtType ExtTy,EVT NewVT) shouldReduceLoadWidth() argument
/llvm-project/llvm/lib/CodeGen/
H A DTypePromotion.cpp112 IntegerType *ExtTy = nullptr; member in __anon559c11500111::IRPromoter
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H A DCodeGenPrepare.cpp4379 ExtType ExtTy = IsSExt ? SignExtension : ZeroExtension; addPromotedInst() local
4401 ExtType ExtTy = IsSExt ? SignExtension : ZeroExtension; getOrigType() local
4613 Type *ExtTy = Ext->getType(); getAction() local
6035 Type *ExtTy = FirstUser->getType(); hasSameExtUse() local
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/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp593 LLT ExtTy = buildCopyToRegs() local
H A DCombinerHelper.cpp4079 LLT ExtTy = MRI.getType(DstReg); applyExtendThroughPhis() local
/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1589 LLT MidTy, ExtTy; legalizeIntrinsic() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp343 LLT ExtTy = getLLTForType(*RetInfo.Ty, DL); lowerReturnVal() local
H A DAMDGPUISelLowering.cpp823 ISD::LoadExtType ExtTy, in shouldReduceLoadWidth() argument
/llvm-project/llvm/utils/TableGen/
H A DGlobalISelEmitter.cpp1553 const TypeSetByHwMode &ExtTy = Dst.getExtType(I); importExplicitDefRenderers() local
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp2451 MVT ExtTy = MVT::getVectorVT(MVT::i16, Ty.getVectorNumElements()); LowerVECTOR_SHIFT() local
3841 shouldReduceLoadWidth(SDNode * Load,ISD::LoadExtType ExtTy,EVT NewVT) const shouldReduceLoadWidth() argument
H A DHexagonISelLoweringHVX.cpp890 MVT ExtTy = ty(ExtVec); in buildHvxVectorReg() local
/llvm-project/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp541 auto *ExtTy = FixedVectorType::getExtendedElementVectorType(ArgTy); simplifyX86pmulh() local
H A DX86ISelLowering.cpp3105 shouldReduceLoadWidth(SDNode * Load,ISD::LoadExtType ExtTy,EVT NewVT) const shouldReduceLoadWidth() argument
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/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp2265 CreateReg(unsigned RegNum,RegKind Kind,SMLoc S,SMLoc E,MCContext & Ctx,RegConstraintEqualityTy EqTy=RegConstraintEqualityTy::EqualsReg,AArch64_AM::ShiftExtendType ExtTy=AArch64_AM::LSL,unsigned ShiftAmount=0,unsigned HasExplicitAmount=false) CreateReg() argument
2284 CreateVectorReg(unsigned RegNum,RegKind Kind,unsigned ElementWidth,SMLoc S,SMLoc E,MCContext & Ctx,AArch64_AM::ShiftExtendType ExtTy=AArch64_AM::LSL,unsigned ShiftAmount=0,unsigned HasExplicitAmount=false) CreateVectorReg() argument
/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp2325 Type *ExtTy = Type::getInt32Ty(C); upgradeX86IntrinsicCall() local
/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DAddressSanitizer.cpp1470 Type *ExtTy = VectorType::get(IntptrTy, cast<VectorType>(Ty)); getInterestingMemoryOperands() local
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp9560 getMaskedLoad(EVT VT,const SDLoc & dl,SDValue Chain,SDValue Base,SDValue Offset,SDValue Mask,SDValue PassThru,EVT MemVT,MachineMemOperand * MMO,ISD::MemIndexedMode AM,ISD::LoadExtType ExtTy,bool isExpanding) getMaskedLoad() argument
9654 getMaskedGather(SDVTList VTs,EVT MemVT,const SDLoc & dl,ArrayRef<SDValue> Ops,MachineMemOperand * MMO,ISD::MemIndexType IndexType,ISD::LoadExtType ExtTy) getMaskedGather() argument
H A DDAGCombiner.cpp22234 ISD::LoadExtType ExtTy = scalarizeExtractedVectorLoad() local
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/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4935 addRequiredExtensionForVectorMULL(SDValue N,SelectionDAG & DAG,const EVT & OrigTy,const EVT & ExtTy,unsigned ExtOpcode) addRequiredExtensionForVectorMULL() argument
15489 shouldReduceLoadWidth(SDNode * Load,ISD::LoadExtType ExtTy,EVT NewVT) const shouldReduceLoadWidth() argument
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/llvm-project/llvm/lib/Analysis/
H A DScalarEvolution.cpp3459 getZeroExtendExpr(AR, ExtTy) == in getUDivExpr() local
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/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp9525 AddRequiredExtensionForVMULL(SDValue N,SelectionDAG & DAG,const EVT & OrigTy,const EVT & ExtTy,unsigned ExtOpcode) AddRequiredExtensionForVMULL() argument