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Searched defs:Defs (Results 1 – 25 of 67) sorted by relevance

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/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFormMemoryClauses.cpp150 bool SIFormMemoryClauses::canBundle(const MachineInstr &MI, const RegUse &Defs, in canBundle() argument
217 RegUse &Defs, RegUse &Uses) const { in collectRegUses() argument
245 if (!canBundle(MI, Defs, Uses)) in processRegUses() argument
301 RegUse Defs, Uses; runOnMachineFunction() local
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H A DSIPostRABundler.cpp49 SmallSet<Register, 16> Defs; member in __anon986ec1e70111::SIPostRABundler
H A DSIFixSGPRCopies.cpp574 auto &Defs = Init.second; in hoistAndMergeSGPRInits() local
469 auto &Defs = Init.second; hoistAndMergeSGPRInits() local
561 auto &Defs = Init.second; hoistAndMergeSGPRInits() local
H A DSIFoldOperands.cpp658 getRegSeqInit(SmallVectorImpl<std::pair<MachineOperand *,unsigned>> & Defs,Register UseReg,uint8_t OpTy) const getRegSeqInit() argument
728 SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs; tryToFoldACImm() local
908 SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs; foldOperand() local
1769 SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs; tryFoldRegSequence() local
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/llvm-project/clang/utils/TableGen/
H A DClangDataCollectorsEmitter.cpp8 const auto &Defs = RK.getClasses(); EmitClangDataCollectors() local
H A DSveEmitter.cpp1242 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createCoreHeaderIntrinsics() local
1446 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createBuiltins() local
1488 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createCodeGenMap() local
1521 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createRangeChecks() local
1651 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createSMEBuiltins() local
1679 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createSMECodeGenMap() local
1713 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createSMERangeChecks() local
1749 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createBuiltinZAState() local
1789 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; createStreamingAttrs() local
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H A DNeonEmitter.cpp2006 genBuiltinsDef(raw_ostream & OS,SmallVectorImpl<Intrinsic * > & Defs) genBuiltinsDef() argument
2040 genStreamingSVECompatibleList(raw_ostream & OS,SmallVectorImpl<Intrinsic * > & Defs) genStreamingSVECompatibleList() argument
2066 genOverloadTypeCheckCode(raw_ostream & OS,SmallVectorImpl<Intrinsic * > & Defs) genOverloadTypeCheckCode() argument
2146 genIntrinsicRangeCheckCode(raw_ostream & OS,SmallVectorImpl<Intrinsic * > & Defs) genIntrinsicRangeCheckCode() argument
2236 SmallVector<Intrinsic *, 128> Defs; runHeader() local
2395 SmallVector<Intrinsic *, 128> Defs; run() local
2503 SmallVector<Intrinsic *, 128> Defs; runFP16() local
2612 SmallVector<Intrinsic *, 128> Defs; runBF16() local
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H A DRISCVVEmitter.cpp417 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; createBuiltins() local
448 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; createCodeGen() local
747 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; createSema() local
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/llvm-project/llvm/tools/llvm-exegesis/lib/
H A DParallelSnippetGenerator.cpp149 const BitVector &Uses, const BitVector &Defs, const InstructionTemplate &IT, in generateSingleRegisterForInstrAvoidingDefUseOverlap() argument
217 BitVector &Uses, BitVector &Defs, InstructionTemplate IT, in generateSingleSnippetForInstrAvoidingDefUseOverlap() argument
276 BitVector Defs(State.getRegInfo().getNumRegs()); in generateSnippetForInstrAvoidingDefUseOverlap() local
H A DMCInstrDescView.h206 SmallVector<RegisterOperandAssignment, 1> Defs; // Unlikely size() > 1. global() member
/llvm-project/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp137 MoveCopyOutOfITBlock(MachineInstr * MI,ARMCC::CondCodes CC,ARMCC::CondCodes OCC,RegisterSet & Defs,RegisterSet & Uses) MoveCopyOutOfITBlock() argument
195 RegisterSet Defs, Uses; InsertITInstructions() local
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H A DA15SDOptimizer.cpp398 SmallVector<unsigned, 8> Defs; getReadDPRs() local
591 SmallVector<unsigned, 8> Defs = getReadDPRs(MI); runOnInstruction() local
/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp433 HandlePhysRegDef(Register Reg,MachineInstr * MI,SmallVectorImpl<unsigned> & Defs) HandlePhysRegDef() argument
472 UpdatePhysRegDefs(MachineInstr & MI,SmallVectorImpl<unsigned> & Defs) UpdatePhysRegDefs() argument
483 runOnInstr(MachineInstr & MI,SmallVectorImpl<unsigned> & Defs,unsigned NumRegs) runOnInstr() argument
547 SmallVector<unsigned, 4> Defs; runOnBlock() local
827 DenseSet<unsigned> Defs, Kills; addNewBlock() local
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H A DRDFLiveness.cpp168 SmallSet<NodeId, 32> Defs; in getAllReachingDefs() local
305 NodeSet &Visited, const NodeSet &Defs) { in getAllReachingDefsRec() argument
311 NodeSet &Visited, const NodeSet &Defs, in getAllReachingDefsRecImpl() argument
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H A DMachineInstrBundle.cpp145 SmallVector<MachineOperand*, 4> Defs; in finalizeBundle() local
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp100 BitVector Defs, Uses; global() member
158 getDefsUses(const MachineInstr * MI,BitVector & Defs,BitVector & Uses) const getDefsUses() argument
182 BitVector Defs(NR), Uses(NR); buildMaps() local
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H A DHexagonExpandCondsets.cpp395 __anonc020511f0702(SetVector<MachineBasicBlock*> &Defs, MachineBasicBlock *Dest) updateDeadsInRange() argument
417 SetVector<MachineBasicBlock*> Defs; updateDeadsInRange() local
818 canMoveOver(MachineInstr & MI,ReferenceMap & Defs,ReferenceMap & Uses) canMoveOver() argument
992 ReferenceMap Uses, Defs; predicate() local
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H A DHexagonRDFOpt.cpp261 NodeList Defs; in rewrite() local
H A DHexagonBitSimplify.cpp299 RegisterSet Defs; in INITIALIZE_PASS_DEPENDENCY() local
318 RegisterSet &Defs) { in getInstrDefs() argument
1498 RegisterSet Defs; in processBlock() local
1626 RegisterSet Defs; processBlock() local
2739 RegisterSet Defs; processBlock() local
2996 RegisterSet Defs; getDefReg() local
3192 RegisterSet Defs; processLoop() local
3258 RegisterSet Defs; processLoop() local
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/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBoolRetToInt.cpp74 SmallPtrSet<Value *, 8> Defs; findAllDefs() local
221 auto Defs = findAllDefs(U); runOnUse() local
/llvm-project/llvm/utils/TableGen/
H A DCTagsEmitter.cpp73 const auto &Defs = Records.getDefs(); in run() local
/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.h48 DenseMap<unsigned, PredSet> Defs; variable
/llvm-project/llvm/lib/Analysis/
H A DMemorySSAUpdater.cpp148 auto *Defs = MSSA->getWritableBlockDefs(MA->getBlock()); in getPreviousDefInBlock() local
175 auto *Defs = MSSA->getWritableBlockDefs(BB); in getPreviousDefFromEnd() local
257 auto *Defs = MSSA->getBlockDefs(MU->getBlock()); in insertUse() local
267 if (auto *Defs = MSSA->getWritableBlockDefs(StartBlock)) { insertUse() local
470 auto *Defs = MSSA->getWritableBlockDefs(NewDef->getBlock()); fixupDefs() local
497 if (auto *Defs = MSSA->getWritableBlockDefs(FixupBlock)) { fixupDefs() local
847 MemorySSA::DefsList *Defs = MSSA->getWritableBlockDefs(BB); applyInsertUpdates() local
1216 auto *Defs = MSSA->getWritableBlockDefs(From); moveAllAccesses() local
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H A DMemorySSA.cpp534 auto *Defs = MSSA.getBlockDefs(Node->getBlock()); in getWalkTarget() local
1539 DefsList *Defs = nullptr; in buildMemorySSA() local
1627 auto *Defs = getOrCreateDefsList(BB); in insertIntoListsForBlock() local
1634 auto *Defs in insertIntoListsForBlock() local
1643 auto *Defs = getOrCreateDefsList(BB); insertIntoListsForBlock() local
1656 auto *Defs = getOrCreateDefsList(BB); insertIntoListsBefore() local
1872 std::unique_ptr<DefsList> &Defs = DefsIt->second; removeFromLists() local
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/llvm-project/llvm/utils/TableGen/Basic/
H A DCodeGenIntrinsics.cpp37 std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic"); CodeGenIntrinsicTable() local

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