/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetRegisterInfo.cpp | 380 shareSameRegisterFile(const TargetRegisterInfo & TRI,const TargetRegisterClass * DefRC,unsigned DefSubReg,const TargetRegisterClass * SrcRC,unsigned SrcSubReg) shareSameRegisterFile() argument 410 shouldRewriteCopySrc(const TargetRegisterClass * DefRC,unsigned DefSubReg,const TargetRegisterClass * SrcRC,unsigned SrcSubReg) const shouldRewriteCopySrc() argument
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H A D | DetectDeadLanes.cpp | 289 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes() local
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H A D | PeepholeOptimizer.cpp | 731 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); findNextSource() local 1293 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); rewriteSource() local
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H A D | RegisterCoalescer.cpp | 1343 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); reMaterializeTrivialDef() local
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/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsInstructionSelector.cpp | 423 const TargetRegisterClass *DefRC = nullptr; in select() local
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/llvm-project/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 221 shouldRewriteCopySrc(const TargetRegisterClass * DefRC,unsigned DefSubReg,const TargetRegisterClass * SrcRC,unsigned SrcSubReg) const shouldRewriteCopySrc() argument
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H A D | X86SpeculativeLoadHardening.cpp | 1959 auto *DefRC = MRI->getRegClass(OldDefReg); hardenPostLoad() local
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/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 936 shouldRewriteCopySrc(const TargetRegisterClass * DefRC,unsigned DefSubReg,const TargetRegisterClass * SrcRC,unsigned SrcSubReg) const shouldRewriteCopySrc() argument
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/llvm-project/llvm/lib/Target/RISCV/GISel/ |
H A D | RISCVInstructionSelector.cpp | 526 const TargetRegisterClass *DefRC = select() local
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/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIRegisterInfo.cpp | 2926 shouldRewriteCopySrc(const TargetRegisterClass * DefRC,unsigned DefSubReg,const TargetRegisterClass * SrcRC,unsigned SrcSubReg) const shouldRewriteCopySrc() argument
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H A D | AMDGPUInstructionSelector.cpp | 221 const TargetRegisterClass *DefRC selectPHI() local
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/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonConstPropagation.cpp | 1952 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg); in evaluate() local
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/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 2465 const TargetRegisterClass *DefRC select() local
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