| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TileShapeInfo.h | 72 for (const MachineOperand &DefMO : MRI->def_operands(Reg)) { deduceImm() local
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveRangeShrink.cpp | 168 const MachineOperand *DefMO = nullptr; runOnMachineFunction() local
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| H A D | CodeGenCommonISel.cpp | 257 for (auto *DefMO : DbgUsers) { salvageDebugInfoForDbgValue() local
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| H A D | InitUndef.cpp | 101 return llvm::any_of(MI.all_defs(), [](const MachineOperand &DefMO) { in isEarlyClobberMI() argument
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| H A D | FixupStatepointCallerSaved.cpp | 486 MachineOperand &DefMO = MI.getOperand(I); in rewriteStatepoint() local
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| H A D | MachineLICM.cpp | 1194 MachineOperand &DefMO = MI.getOperand(i); IsCheapInstruction() local
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| H A D | ScheduleDAGInstrs.cpp | 318 MachineOperand &DefMO = DefInstr->getOperand(I->OpIdx); addPhysRegDeps() local
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| H A D | MachineFunction.cpp | 1205 for (const auto &DefMO : DefMI.operands()) { finalizeDebugInstrRefs() local
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| H A D | MachineInstr.cpp | 1164 MachineOperand &DefMO = getOperand(DefIdx); tieOperands() local
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| H A D | RegisterCoalescer.cpp | 1384 MachineOperand &DefMO = NewMI.getOperand(0); reMaterializeTrivialDef() local
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| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 651 MachineOperand &DefMO = Def->getOperand(0); moveAndTeeForMultiUse() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPeepholeSDWA.cpp | 303 for (auto &DefMO : DefInstr->defs()) { findSingleRegDef() local
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| H A D | SIInstrInfo.h | 1018 isInlineConstant(const MachineInstr & MI,const MachineOperand & UseMO,const MachineOperand & DefMO) isInlineConstant() argument
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| H A D | SIInsertWaitcnts.cpp | 886 MachineOperand &DefMO = Inst.getOperand(I); updateByEvent() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 4370 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); getOperandLatency() local
4400 getOperandLatencyImpl(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MCInstrDesc & DefMCID,unsigned DefAdj,const MachineOperand & DefMO,unsigned Reg,const MachineInstr & UseMI,unsigned UseIdx,const MCInstrDesc & UseMCID,unsigned UseAdj) const getOperandLatencyImpl() argument
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 4333 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); getOperandLatency() local
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 177 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); getOperandLatency() local
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