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Searched defs:DefIdx (Results 1 – 25 of 42) sorted by relevance

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/llvm-project/llvm/lib/CodeGen/
H A DLiveIntervalCalc.cpp35 SlotIndex DefIdx = createDeadDef() local
180 unsigned DefIdx; extendToUses() local
H A DTargetSchedule.cpp202 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency() local
146 unsigned DefIdx = 0; findDefIdx() local
H A DTargetInstrInfo.cpp1443 getOperandLatency(const InstrItineraryData * ItinData,SDNode * DefNode,unsigned DefIdx,SDNode * UseNode,unsigned UseIdx) const getOperandLatency() argument
1645 getOperandLatency(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const getOperandLatency() argument
1652 getRegSequenceInputs(const MachineInstr & MI,unsigned DefIdx,SmallVectorImpl<RegSubRegPairAndIdx> & InputRegs) const getRegSequenceInputs() argument
1679 getExtractSubregInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPairAndIdx & InputReg) const getExtractSubregInputs() argument
1704 getInsertSubregInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPair & BaseReg,RegSubRegPairAndIdx & InsertedReg) const getInsertSubregInputs() argument
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H A DLiveRangeEdit.cpp167 SlotIndex DefIdx; in canRematerializeAt() local
H A DRenameIndependentSubregs.cpp335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags() local
H A DMachineCombiner.cpp232 int DefIdx = getDepth() local
H A DTargetRegisterInfo.cpp389 unsigned SrcIdx, DefIdx; shareSameRegisterFile() local
H A DMachineInstr.cpp280 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); addOperand() local
960 unsigned DefIdx; getRegClassConstraint() local
1163 tieOperands(unsigned DefIdx,unsigned UseIdx) tieOperands() argument
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H A DMachineVerifier.cpp2433 unsigned DefIdx; visitMachineOperand() local
2678 checkLivenessAtDef(const MachineOperand * MO,unsigned MONum,SlotIndex DefIdx,const LiveRange & LR,Register VRegOrUnit,bool SubRangeCheck,LaneBitmask LaneMask) checkLivenessAtDef() argument
2881 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI); checkLiveness() local
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/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h141 unsigned DefIdx = 0; variable
H A DScheduleDAGSDNodes.cpp479 unsigned DefIdx = N->getOperand(i).getResNo(); in AddSchedEdges() local
659 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
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/llvm-project/llvm/include/llvm/MC/
H A DMCInstrItineraries.h186 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding()
208 std::optional<unsigned> getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency()
H A DMCSubtargetInfo.h177 getWriteLatencyEntry(const MCSchedClassDesc * SC,unsigned DefIdx) getWriteLatencyEntry() argument
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp623 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs() local
803 SwapVector[DefIdx] in markSwapsForRemoval() local
727 int DefIdx = SwapMap[DefMI]; recordUnoptimizableWebs() local
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H A DPPCInstrInfo.h343 unsigned DefIdx, in getOperandLatency() argument
352 hasLowDefLatency(const TargetSchedModel & SchedModel,const MachineInstr & DefMI,unsigned DefIdx) hasLowDefLatency() argument
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp567 if (DefIdx >= 0 && OpIdx >= 0 && in runOnMachineFunction() local
399 int DefIdx = mapRegToGPRIndex(MI.getOperand(0).getReg()); handleADRP() local
/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp45 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
/llvm-project/llvm/unittests/Target/AArch64/
H A DAArch64SVESchedPseudoTest.cpp90 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in runSVEPseudoTestForCPU() local
/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h591 unsigned DefIdx = 0; getDefIndex() local
896 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { tryCombineUnmergeDefs() local
1154 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; tryCombineUnmergeValues() local
1202 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { tryCombineUnmergeValues() local
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/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp214 unsigned DefIdx = 0; tryInlineAsm() local
/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3879 getVLDMDefCycle(const InstrItineraryData * ItinData,const MCInstrDesc & DefMCID,unsigned DefClass,unsigned DefIdx,unsigned DefAlign) const getVLDMDefCycle() argument
3919 getLDMDefCycle(const InstrItineraryData * ItinData,const MCInstrDesc & DefMCID,unsigned DefClass,unsigned DefIdx,unsigned DefAlign) const getLDMDefCycle() argument
4019 getOperandLatency(const InstrItineraryData * ItinData,const MCInstrDesc & DefMCID,unsigned DefIdx,unsigned DefAlign,const MCInstrDesc & UseMCID,unsigned UseIdx,unsigned UseAlign) const getOperandLatency() argument
4132 getBundledDefMI(const TargetRegisterInfo * TRI,const MachineInstr * MI,unsigned Reg,unsigned & DefIdx,unsigned & Dist) getBundledDefMI() argument
4365 getOperandLatency(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const getOperandLatency() argument
4399 getOperandLatencyImpl(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MCInstrDesc & DefMCID,unsigned DefAdj,const MachineOperand & DefMO,unsigned Reg,const MachineInstr & UseMI,unsigned UseIdx,const MCInstrDesc & UseMCID,unsigned UseAdj) const getOperandLatencyImpl() argument
4459 getOperandLatency(const InstrItineraryData * ItinData,SDNode * DefNode,unsigned DefIdx,SDNode * UseNode,unsigned UseIdx) const getOperandLatency() argument
4807 hasHighOperandLatency(const TargetSchedModel & SchedModel,const MachineRegisterInfo * MRI,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const hasHighOperandLatency() argument
5453 getRegSequenceLikeInputs(const MachineInstr & MI,unsigned DefIdx,SmallVectorImpl<RegSubRegPairAndIdx> & InputRegs) const getRegSequenceLikeInputs() argument
5480 getExtractSubregLikeInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPairAndIdx & InputReg) const getExtractSubregLikeInputs() argument
5503 getInsertSubregLikeInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPair & BaseReg,RegSubRegPairAndIdx & InsertedReg) const getInsertSubregLikeInputs() argument
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/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp218 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; getLatency() local
/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1378 getRegSequenceLikeInputs(const MachineInstr & MI,unsigned DefIdx,SmallVectorImpl<RegSubRegPairAndIdx> & InputRegs) getRegSequenceLikeInputs() argument
1392 getExtractSubregLikeInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPairAndIdx & InputReg) getExtractSubregLikeInputs() argument
1406 getInsertSubregLikeInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPair & BaseReg,RegSubRegPairAndIdx & InsertedReg) getInsertSubregLikeInputs() argument
1812 hasHighOperandLatency(const TargetSchedModel & SchedModel,const MachineRegisterInfo * MRI,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) hasHighOperandLatency() argument
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/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp383 unsigned DefIdx = OpInfo.getMatchedOperand(); in lowerInlineAsm() local
/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp169 unsigned DefIdx = 0; in selectInlineAsm() local

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