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Searched defs:DefIdx (Results 1 – 25 of 40) sorted by relevance

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/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveIntervalCalc.cpp35 SlotIndex DefIdx = in createDeadDef() local
180 unsigned DefIdx; in extendToUses() local
H A DTargetSchedule.cpp146 unsigned DefIdx = 0; in findDefIdx() local
202 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
H A DTargetInstrInfo.cpp1383 getOperandLatency(const InstrItineraryData * ItinData,SDNode * DefNode,unsigned DefIdx,SDNode * UseNode,unsigned UseIdx) const getOperandLatency() argument
1585 getOperandLatency(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const getOperandLatency() argument
1592 getRegSequenceInputs(const MachineInstr & MI,unsigned DefIdx,SmallVectorImpl<RegSubRegPairAndIdx> & InputRegs) const getRegSequenceInputs() argument
1619 getExtractSubregInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPairAndIdx & InputReg) const getExtractSubregInputs() argument
1644 getInsertSubregInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPair & BaseReg,RegSubRegPairAndIdx & InsertedReg) const getInsertSubregInputs() argument
[all...]
H A DLiveRangeEdit.cpp167 SlotIndex DefIdx; in canRematerializeAt() local
H A DRenameIndependentSubregs.cpp335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags() local
H A DMachineCombiner.cpp235 int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg()); getDepth() local
H A DTargetRegisterInfo.cpp393 unsigned SrcIdx, DefIdx; shareSameRegisterFile() local
H A DMachineInstr.cpp277 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); addOperand() local
919 unsigned DefIdx; getRegClassConstraint() local
1121 tieOperands(unsigned DefIdx,unsigned UseIdx) tieOperands() argument
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H A DMachineVerifier.cpp2208 unsigned DefIdx; visitMachineOperand() local
2453 checkLivenessAtDef(const MachineOperand * MO,unsigned MONum,SlotIndex DefIdx,const LiveRange & LR,Register VRegOrUnit,bool SubRangeCheck,LaneBitmask LaneMask) checkLivenessAtDef() argument
2656 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI); checkLiveness() local
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/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h141 unsigned DefIdx = 0; variable
H A DScheduleDAGSDNodes.cpp478 unsigned DefIdx = N->getOperand(i).getResNo(); AddSchedEdges() local
658 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); computeOperandLatency() local
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrItineraries.h186 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding()
208 std::optional<unsigned> getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency()
H A DMCSubtargetInfo.h177 unsigned DefIdx) const { in getWriteLatencyEntry() argument
/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp623 int DefIdx = SwapMap[DefMI]; in formWebs() local
727 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
803 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
H A DPPCInstrInfo.h339 unsigned DefIdx, in hasLowDefLatency() argument
330 getOperandLatency(const InstrItineraryData * ItinData,SDNode * DefNode,unsigned DefIdx,SDNode * UseNode,unsigned UseIdx) getOperandLatency() argument
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp399 int DefIdx = mapRegToGPRIndex(MI.getOperand(0).getReg()); in handleADRP() local
567 int DefIdx = mapRegToGPRIndex(Def.getReg()); in runOnMachineFunction() local
/freebsd-src/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp45 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h573 unsigned DefIdx = 0; getDefIndex() local
878 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { tryCombineUnmergeDefs() local
1135 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; tryCombineUnmergeValues() local
1183 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { tryCombineUnmergeValues() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp208 unsigned DefIdx = 0; tryInlineAsm() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3878 getVLDMDefCycle(const InstrItineraryData * ItinData,const MCInstrDesc & DefMCID,unsigned DefClass,unsigned DefIdx,unsigned DefAlign) const getVLDMDefCycle() argument
3918 getLDMDefCycle(const InstrItineraryData * ItinData,const MCInstrDesc & DefMCID,unsigned DefClass,unsigned DefIdx,unsigned DefAlign) const getLDMDefCycle() argument
4018 getOperandLatency(const InstrItineraryData * ItinData,const MCInstrDesc & DefMCID,unsigned DefIdx,unsigned DefAlign,const MCInstrDesc & UseMCID,unsigned UseIdx,unsigned UseAlign) const getOperandLatency() argument
4131 getBundledDefMI(const TargetRegisterInfo * TRI,const MachineInstr * MI,unsigned Reg,unsigned & DefIdx,unsigned & Dist) getBundledDefMI() argument
4364 getOperandLatency(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const getOperandLatency() argument
4398 getOperandLatencyImpl(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MCInstrDesc & DefMCID,unsigned DefAdj,const MachineOperand & DefMO,unsigned Reg,const MachineInstr & UseMI,unsigned UseIdx,const MCInstrDesc & UseMCID,unsigned UseAdj) const getOperandLatencyImpl() argument
4458 getOperandLatency(const InstrItineraryData * ItinData,SDNode * DefNode,unsigned DefIdx,SDNode * UseNode,unsigned UseIdx) const getOperandLatency() argument
4806 hasHighOperandLatency(const TargetSchedModel & SchedModel,const MachineRegisterInfo * MRI,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const hasHighOperandLatency() argument
5452 getRegSequenceLikeInputs(const MachineInstr & MI,unsigned DefIdx,SmallVectorImpl<RegSubRegPairAndIdx> & InputRegs) const getRegSequenceLikeInputs() argument
5479 getExtractSubregLikeInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPairAndIdx & InputReg) const getExtractSubregLikeInputs() argument
5502 getInsertSubregLikeInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPair & BaseReg,RegSubRegPairAndIdx & InsertedReg) const getInsertSubregLikeInputs() argument
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1342 getRegSequenceLikeInputs(const MachineInstr & MI,unsigned DefIdx,SmallVectorImpl<RegSubRegPairAndIdx> & InputRegs) getRegSequenceLikeInputs() argument
1356 getExtractSubregLikeInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPairAndIdx & InputReg) getExtractSubregLikeInputs() argument
1370 getInsertSubregLikeInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPair & BaseReg,RegSubRegPairAndIdx & InsertedReg) getInsertSubregLikeInputs() argument
1776 hasHighOperandLatency(const TargetSchedModel & SchedModel,const MachineRegisterInfo * MRI,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) hasHighOperandLatency() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp218 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in getLatency() local
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp383 unsigned DefIdx = OpInfo.getMatchedOperand(); in lowerInlineAsm() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp162 unsigned DefIdx = 0; selectInlineAsm() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp563 int DefIdx = -1; restoreLatency() local

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