Lines Matching defs:DefIdx

3879                                   unsigned DefIdx, unsigned DefAlign) const {
3880   int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3883     return ItinData->getOperandCycle(DefClass, DefIdx);
3919                                  unsigned DefIdx, unsigned DefAlign) const {
3920   int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3923     return ItinData->getOperandCycle(DefClass, DefIdx);
4019     unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID,
4024   if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
4025     return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
4034     DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4043     DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
4064     DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
4116       // It's a variable_ops instruction so we can't use DefIdx here. Just use
4121     } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
4132                                            unsigned &DefIdx, unsigned &Dist) {
4149   DefIdx = Idx;
4365     unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {
4370   const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4377         getBundledDefMI(&getRegisterInfo(), &DefMI, Reg, DefIdx, DefAdj);
4393       ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,
4399     unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
4440       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);
4459                                     SDNode *DefNode, unsigned DefIdx,
4474         ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
4490       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);
4521   } else if (DefIdx == 0 && Latency > 2U && Subtarget.isSwift()) {
4807                                              unsigned DefIdx,
4818       SchedModel.computeOperandLatency(&DefMI, DefIdx, &UseMI, UseIdx);
4827                                         unsigned DefIdx) const {
4836         ItinData->getOperandCycle(DefClass, DefIdx);
5453     const MachineInstr &MI, unsigned DefIdx,
5455   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
5480     const MachineInstr &MI, unsigned DefIdx,
5482   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
5496     InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
5503     const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
5505   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");