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Searched defs:DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE (Results 1 – 3 of 3) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_enum.h429 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x9, enumerator
H A Ddce_11_2_enum.h1601 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x9, enumerator
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/
H A Dvega10_enum.h12220 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x00000009, enumerator