| /llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelDAGToDAG.cpp | 232 replaceInChain(SelectionDAG * CurDAG,SDValue Chain,SDValue Old,SDValue New) replaceInChain() argument
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 907 narrowIfNeeded(SelectionDAG * CurDAG,SDValue N) narrowIfNeeded() argument
1188 Widen(SelectionDAG * CurDAG,SDValue N) Widen() argument
2346 isBitfieldExtractOpFromAnd(SelectionDAG * CurDAG,SDNode * N,unsigned & Opc,SDValue & Opd0,unsigned & LSB,unsigned & MSB,unsigned NumberOfIgnoredLowBits,bool BiggerPattern) isBitfieldExtractOpFromAnd() argument
2604 isBitfieldExtractOp(SelectionDAG * CurDAG,SDNode * N,unsigned & Opc,SDValue & Opd0,unsigned & Immr,unsigned & Imms,unsigned NumberOfIgnoredLowBits=0,bool BiggerPattern=false) isBitfieldExtractOp() argument
2911 getLeftShift(SelectionDAG * CurDAG,SDValue Op,int ShlAmount) getLeftShift() argument
2955 isBitfieldPositioningOp(SelectionDAG * CurDAG,SDValue Op,bool BiggerPattern,SDValue & Src,int & DstLSB,int & Width) isBitfieldPositioningOp() argument
2985 isBitfieldPositioningOpFromAnd(SelectionDAG * CurDAG,SDValue Op,bool BiggerPattern,const uint64_t NonZeroBits,SDValue & Src,int & DstLSB,int & Width) isBitfieldPositioningOpFromAnd() argument
3107 isBitfieldPositioningOpFromShl(SelectionDAG * CurDAG,SDValue Op,bool BiggerPattern,const uint64_t NonZeroBits,SDValue & Src,int & DstLSB,int & Width) isBitfieldPositioningOpFromShl() argument
3148 tryBitfieldInsertOpFromOrAndImm(SDNode * N,SelectionDAG * CurDAG) tryBitfieldInsertOpFromOrAndImm() argument
3236 isWorthFoldingIntoOrrWithShift(SDValue Dst,SelectionDAG * CurDAG,SDValue & ShiftedOperand,uint64_t & EncodedShiftImm) isWorthFoldingIntoOrrWithShift() argument
3312 tryOrrWithShift(SDNode * N,SDValue OrOpd0,SDValue OrOpd1,SDValue Src,SDValue Dst,SelectionDAG * CurDAG,const bool BiggerPattern) tryOrrWithShift() argument
3412 tryBitfieldInsertOpFromOr(SDNode * N,const APInt & UsefulBits,SelectionDAG * CurDAG) tryBitfieldInsertOpFromOr() argument
3760 checkCVTFixedPointOperandWithFBits(SelectionDAG * CurDAG,SDValue N,SDValue & FixedPos,unsigned RegWidth,bool isReciprocal) checkCVTFixedPointOperandWithFBits() argument
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| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 699 isThreadPointerAcquisitionNode(SDValue Base,SelectionDAG * CurDAG) isThreadPointerAcquisitionNode() argument
743 canOptimizeTLSDFormToXForm(SelectionDAG * CurDAG,SDValue Base) canOptimizeTLSDFormToXForm() argument
952 allUsesTruncate(SelectionDAG * CurDAG,SDNode * N) allUsesTruncate() argument
1019 selectI64ImmDirect(SelectionDAG * CurDAG,const SDLoc & dl,uint64_t Imm,unsigned & InstCnt) selectI64ImmDirect() argument
1260 selectI64ImmDirectPrefix(SelectionDAG * CurDAG,const SDLoc & dl,uint64_t Imm,unsigned & InstCnt) selectI64ImmDirectPrefix() argument
1380 selectI64Imm(SelectionDAG * CurDAG,const SDLoc & dl,uint64_t Imm,unsigned * InstCnt=nullptr) selectI64Imm() argument
1486 selectI64Imm(SelectionDAG * CurDAG,SDNode * N) selectI64Imm() argument
2825 SelectionDAG *CurDAG = nullptr; global() member in __anona2527ef30711::BitPermutationSelector
2881 SelectionDAG *CurDAG; global() member in __anona2527ef30711::IntegerCompareEliminator
3979 allUsesExtend(SDValue Compare,SelectionDAG * CurDAG) allUsesExtend() argument
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1857 SelectSAddrFI(SelectionDAG * CurDAG,SDValue SAddr) SelectSAddrFI() argument
3129 buildRegSequence32(SmallVectorImpl<SDValue> & Elts,llvm::SelectionDAG * CurDAG,const SDLoc & DL) buildRegSequence32() argument
3161 buildRegSequence16(SmallVectorImpl<SDValue> & Elts,llvm::SelectionDAG * CurDAG,const SDLoc & DL) buildRegSequence16() argument
3187 buildRegSequence(SmallVectorImpl<SDValue> & Elts,llvm::SelectionDAG * CurDAG,const SDLoc & DL,unsigned ElementSize) buildRegSequence() argument
3198 selectWMMAModsNegAbs(unsigned ModOpcode,unsigned & Mods,SmallVectorImpl<SDValue> & Elts,SDValue & Src,llvm::SelectionDAG * CurDAG,const SDLoc & DL,unsigned ElementSize) selectWMMAModsNegAbs() argument
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| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 175 selectImmSeq(SelectionDAG * CurDAG,const SDLoc & DL,const MVT VT,RISCVMatInt::InstSeq & Seq) selectImmSeq() argument
204 selectImm(SelectionDAG * CurDAG,const SDLoc & DL,const MVT VT,int64_t Imm,const RISCVSubtarget & Subtarget) selectImm() argument
239 createTuple(SelectionDAG & CurDAG,ArrayRef<SDValue> Regs,unsigned NF,RISCVII::VLMUL LMUL) createTuple() argument
2446 selectConstantAddr(SelectionDAG * CurDAG,const SDLoc & DL,const MVT VT,const RISCVSubtarget * Subtarget,SDValue Addr,SDValue & Base,SDValue & Offset,bool IsPrefetch=false) selectConstantAddr() argument
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGISel.h | 52 SelectionDAG *CurDAG; global() variable
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| /llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 2240 pickOpcodeForVectorStParam(SmallVector<SDValue,8> & Ops,unsigned NumElts,MVT::SimpleValueType MemTy,SelectionDAG * CurDAG,SDLoc DL) pickOpcodeForVectorStParam() argument
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| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 1304 isFusableLoadOpStorePattern(StoreSDNode * StoreNode,SDValue StoredVal,SelectionDAG * CurDAG,LoadSDNode * & LoadNode,SDValue & InputChain) isFusableLoadOpStorePattern() argument
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 800 moveBelowOrigChain(SelectionDAG * CurDAG,SDValue Load,SDValue Call,SDValue OrigChain) moveBelowOrigChain() argument
3425 isFusableLoadOpStorePattern(StoreSDNode * StoreNode,SDValue StoredVal,SelectionDAG * CurDAG,unsigned LoadOpNo,LoadSDNode * & LoadNode,SDValue & InputChain) isFusableLoadOpStorePattern() argument
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1586 getAL(SelectionDAG * CurDAG,const SDLoc & dl) getAL() argument
5371 getIntOperandsFromRegisterString(StringRef RegString,SelectionDAG * CurDAG,const SDLoc & DL,std::vector<SDValue> & Ops) getIntOperandsFromRegisterString() argument
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGISel.cpp | 2682 HandleMergeInputChains(SmallVectorImpl<SDNode * > & ChainNodesMatched,SelectionDAG * CurDAG) HandleMergeInputChains() argument
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| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 984 performMADD_MSUBCombine(SDNode * ROOTNode,SelectionDAG & CurDAG,const MipsSubtarget & Subtarget) performMADD_MSUBCombine() argument
|