| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 951 buildAtomicCmpXchgWithSuccess(const DstOp & OldValRes,const DstOp & SuccessRes,const SrcOp & Addr,const SrcOp & CmpVal,const SrcOp & NewVal,MachineMemOperand & MMO) buildAtomicCmpXchgWithSuccess() argument
979 buildAtomicCmpXchg(const DstOp & OldValRes,const SrcOp & Addr,const SrcOp & CmpVal,const SrcOp & NewVal,MachineMemOperand & MMO) buildAtomicCmpXchg() argument
|
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 2763 getTestUnderMaskCond(unsigned BitSize,unsigned CCMask,uint64_t Mask,uint64_t CmpVal,unsigned ICmpType) getTestUnderMaskCond() argument
2880 uint64_t CmpVal = ConstOp1->getZExtValue(); adjustForTestUnderMask() local
4675 SDValue CmpVal = Node->getOperand(2); lowerATOMIC_CMP_SWAP() local
8764 Register CmpVal = MI.getOperand(3).getReg(); emitAtomicCmpSwapW() local
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCodeGenPrepare.cpp | 1691 Value *CmpVal; visitSelectInst() local
|
| H A D | AMDGPULegalizerInfo.cpp | 3199 Register CmpVal = MI.getOperand(2).getReg(); legalizeAtomicCmpXChg() local
6162 Register CmpVal; legalizeBufferAtomic() local
|
| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 479 double CmpVal = IsUnsigned ? -(double)Limit * 2.0 : -(double)Limit; LowerFPToInt() local
|
| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4636 emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase & Builder,AtomicCmpXchgInst * CI,Value * AlignedAddr,Value * CmpVal,Value * NewVal,Value * Mask,AtomicOrdering Ord) const emitMaskedAtomicCmpXchgIntrinsic() argument
|
| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1948 Register CmpVal = MI.getOperand(2).getReg(); emitAtomicCmpSwapPartword() local
|
| /llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 5693 APInt CmpVal = APInt::getOneBitSet(TypeBits, ShAmt); foldICmpEquality() local
|
| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2218 emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase & Builder,AtomicCmpXchgInst * CI,Value * AlignedAddr,Value * CmpVal,Value * NewVal,Value * Mask,AtomicOrdering Ord) emitMaskedAtomicCmpXchgIntrinsic() argument
|
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 3531 isUndefOrEqual(int Val,int CmpVal) isUndefOrEqual() argument
3537 isUndefOrEqual(ArrayRef<int> Mask,int CmpVal) isUndefOrEqual() argument
3545 isUndefOrEqualInRange(ArrayRef<int> Mask,int CmpVal,unsigned Pos,unsigned Size) isUndefOrEqualInRange() argument
46904 const APInt &CmpVal = CmpConstant->getAPIntValue(); combineSetCCMOVMSK() local
[all...] |
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 18839 emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase & Builder,AtomicCmpXchgInst * CI,Value * AlignedAddr,Value * CmpVal,Value * NewVal,Value * Mask,AtomicOrdering Ord) const emitMaskedAtomicCmpXchgIntrinsic() argument
|
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 21046 emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase & Builder,AtomicCmpXchgInst * CI,Value * AlignedAddr,Value * CmpVal,Value * NewVal,Value * Mask,AtomicOrdering Ord) const emitMaskedAtomicCmpXchgIntrinsic() argument
|