| /llvm-project/clang/test/CodeGen/ |
| H A D | arm-vector-align.c | 13 typedef float AlignedAddr __attribute__ ((aligned (16))); typedef
|
| /llvm-project/llvm/include/llvm/Support/ |
| H A D | Allocator.h | 191 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); AllocateSlow() local
201 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); AllocateSlow() local
|
| /llvm-project/clang/test/Analysis/inlining/ |
| H A D | placement-new-fp-suppression.cpp | 57 uintptr_t AlignedAddr = alignAddr(Allocator.Allocate(PaddedSize, 0), in Allocate() local
|
| /llvm-project/llvm/lib/CodeGen/ |
| H A D | AtomicExpandPass.cpp | 684 Value *AlignedAddr = nullptr; global() member
[all...] |
| /llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4635 emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase & Builder,AtomicCmpXchgInst * CI,Value * AlignedAddr,Value * CmpVal,Value * NewVal,Value * Mask,AtomicOrdering Ord) const emitMaskedAtomicCmpXchgIntrinsic() argument
4656 emitMaskedAtomicRMWIntrinsic(IRBuilderBase & Builder,AtomicRMWInst * AI,Value * AlignedAddr,Value * Incr,Value * Mask,Value * ShiftAmt,AtomicOrdering Ord) const emitMaskedAtomicRMWIntrinsic() argument
[all...] |
| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1702 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); emitAtomicBinaryPartword() local
1951 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); emitAtomicCmpSwapPartword() local
|
| /llvm-project/compiler-rt/lib/sanitizer_common/tests/ |
| H A D | sanitizer_allocator_test.cpp | 305 uptr AlignedAddr; global() member in ScopedPremappedHeap
|
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 4564 getCSAddressAndShifts(SDValue Addr,SelectionDAG & DAG,SDLoc DL,SDValue & AlignedAddr,SDValue & BitShift,SDValue & NegBitShift) getCSAddressAndShifts() argument
4613 SDValue AlignedAddr, BitShift, NegBitShift; lowerATOMIC_LOAD_OP() local
4709 SDValue AlignedAddr, BitShift, NegBitShift; lowerATOMIC_CMP_SWAP() local
|
| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2182 emitMaskedAtomicRMWIntrinsic(IRBuilderBase & Builder,AtomicRMWInst * AI,Value * AlignedAddr,Value * Incr,Value * Mask,Value * ShiftAmt,AtomicOrdering Ord) emitMaskedAtomicRMWIntrinsic() argument
2217 emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase & Builder,AtomicCmpXchgInst * CI,Value * AlignedAddr,Value * CmpVal,Value * NewVal,Value * Mask,AtomicOrdering Ord) emitMaskedAtomicCmpXchgIntrinsic() argument
|
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 18816 emitMaskedAtomicRMWIntrinsic(IRBuilderBase & Builder,AtomicRMWInst * AI,Value * AlignedAddr,Value * Incr,Value * Mask,Value * ShiftAmt,AtomicOrdering Ord) const emitMaskedAtomicRMWIntrinsic() argument
18838 emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase & Builder,AtomicCmpXchgInst * CI,Value * AlignedAddr,Value * CmpVal,Value * NewVal,Value * Mask,AtomicOrdering Ord) const emitMaskedAtomicCmpXchgIntrinsic() argument
|
| /llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 20972 emitMaskedAtomicRMWIntrinsic(IRBuilderBase & Builder,AtomicRMWInst * AI,Value * AlignedAddr,Value * Incr,Value * Mask,Value * ShiftAmt,AtomicOrdering Ord) const emitMaskedAtomicRMWIntrinsic() argument
21045 emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase & Builder,AtomicCmpXchgInst * CI,Value * AlignedAddr,Value * CmpVal,Value * NewVal,Value * Mask,AtomicOrdering Ord) const emitMaskedAtomicCmpXchgIntrinsic() argument
|