Lines Matching defs:hp
73 #define HREAD1(hp, reg) \
74 (sdhc_read_1((hp), (reg)))
75 #define HREAD2(hp, reg) \
76 (sdhc_read_2((hp), (reg)))
77 #define HREAD4(hp, reg) \
78 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg)))
79 #define HWRITE1(hp, reg, val) \
80 sdhc_write_1((hp), (reg), (val))
81 #define HWRITE2(hp, reg, val) \
82 sdhc_write_2((hp), (reg), (val))
83 #define HWRITE4(hp, reg, val) \
84 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val))
85 #define HCLR1(hp, reg, bits) \
86 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits))
87 #define HCLR2(hp, reg, bits) \
88 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits))
89 #define HSET1(hp, reg, bits) \
90 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits))
91 #define HSET2(hp, reg, bits) \
92 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits))
160 sdhc_read_1(struct sdhc_host *hp, bus_size_t offset)
164 if (hp->flags & SHF_USE_32BIT_ACCESS) {
165 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3);
169 return bus_space_read_1(hp->iot, hp->ioh, offset);
173 sdhc_read_2(struct sdhc_host *hp, bus_size_t offset)
177 if (hp->flags & SHF_USE_32BIT_ACCESS) {
178 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2);
182 return bus_space_read_2(hp->iot, hp->ioh, offset);
186 sdhc_write_1(struct sdhc_host *hp, bus_size_t offset, uint8_t value)
190 if (hp->flags & SHF_USE_32BIT_ACCESS) {
191 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3);
194 bus_space_write_4(hp->iot, hp->ioh, offset & ~3, reg);
198 bus_space_write_1(hp->iot, hp->ioh, offset, value);
202 sdhc_write_2(struct sdhc_host *hp, bus_size_t offset, uint16_t value)
206 if (hp->flags & SHF_USE_32BIT_ACCESS) {
209 hp->block_size = value;
212 hp->block_count = value;
215 hp->transfer_mode = value;
218 bus_space_write_4(hp->iot, hp->ioh, SDHC_BLOCK_SIZE,
219 (hp->block_count << 16) | hp->block_size);
220 bus_space_write_4(hp->iot, hp->ioh, SDHC_TRANSFER_MODE,
221 (value << 16) | hp->transfer_mode);
225 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2);
228 bus_space_write_4(hp->iot, hp->ioh, offset & ~2, reg);
232 bus_space_write_2(hp->iot, hp->ioh, offset, value);
245 struct sdhc_host *hp;
253 hp = malloc(sizeof(*hp), M_DEVBUF, M_WAITOK | M_ZERO);
254 sc->sc_host[sc->sc_nhosts - 1] = hp;
257 SET(hp->flags, SHF_USE_32BIT_ACCESS);
260 hp->sc = sc;
261 hp->iot = iot;
262 hp->ioh = ioh;
265 hp->version = HREAD2(hp, SDHC_HOST_CTL_VERSION);
270 (void)sdhc_host_reset(hp);
273 caps = HREAD4(hp, SDHC_CAPABILITIES);
279 SET(hp->flags, SHF_USE_DMA);
281 SET(hp->flags, SHF_USE_DMA64);
287 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) {
291 hp->clkbase = SDHC_BASE_FREQ_KHZ_V3(caps);
296 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps);
298 if (hp->clkbase == 0) {
301 hp->clkbase = sc->sc_clkbase;
303 if (hp->clkbase == 0) {
308 } else if (hp->clkbase < 10000 || hp->clkbase > max_clock) {
310 sc->sc_dev.dv_xname, hp->clkbase / 1000);
314 switch (SDHC_SPEC_VERSION(hp->version)) {
322 major = SDHC_SPEC_VERSION(hp->version) + 1, minor = 0;
327 major, minor, hp->clkbase / 1000);
338 SET(hp->ocr, MMC_OCR_1_65V_1_95V);
340 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V);
342 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V);
350 hp->maxblklen = 512;
353 hp->maxblklen = 1024;
356 hp->maxblklen = 2048;
359 hp->maxblklen = 1;
363 if (ISSET(hp->flags, SHF_USE_DMA)) {
368 PAGE_SIZE, hp->adma_segs, 1, &rseg,
372 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg,
373 PAGE_SIZE, &hp->adma2, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
375 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg);
379 0, BUS_DMA_WAITOK, &hp->adma_map);
381 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE);
382 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg);
385 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map,
386 hp->adma2, PAGE_SIZE, NULL,
389 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map);
390 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE);
391 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg);
398 DEVNAME(hp->sc));
399 CLR(hp->flags, SHF_USE_DMA);
410 saa.sch = hp;
414 if (ISSET(hp->flags, SHF_USE_DMA))
422 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) {
423 uint32_t caps2 = HREAD4(hp, SDHC_CAPABILITIES2);
437 hp->sdmmc = config_found(&sc->sc_dev, &saa, NULL);
438 if (hp->sdmmc == NULL) {
446 free(hp, M_DEVBUF, sizeof *hp);
456 struct sdhc_host *hp;
465 hp = sc->sc_host[n];
466 for (i = 0; i < sizeof hp->regs; i++)
467 hp->regs[i] = HREAD1(hp, i);
473 hp = sc->sc_host[n];
474 (void)sdhc_host_reset(hp);
475 for (i = 0; i < sizeof hp->regs; i++)
476 HWRITE1(hp, i, hp->regs[i]);
498 struct sdhc_host *hp;
503 hp = sc->sc_host[i];
504 (void)sdhc_host_reset(hp);
515 struct sdhc_host *hp = sch;
523 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0);
529 if ((error = sdhc_soft_reset(hp, SDHC_RESET_ALL)) != 0) {
535 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX);
543 HWRITE2(hp, SDHC_NINTR_STATUS_EN, imask);
544 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK);
545 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, imask);
546 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK);
555 struct sdhc_host *hp = sch;
556 return hp->ocr;
562 struct sdhc_host *hp = sch;
563 return hp->maxblklen;
572 struct sdhc_host *hp = sch;
574 if (hp->sc->sc_card_detect)
575 return hp->sc->sc_card_detect(hp->sc);
577 return ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED) ?
588 struct sdhc_host *hp = sch;
596 HWRITE1(hp, SDHC_POWER_CTL, 0);
598 (void)sdhc_host_reset(hp);
605 ocr &= hp->ocr;
621 if (HREAD1(hp, SDHC_POWER_CTL) ==
630 if (!(hp->sc->sc_flags & SDHC_F_NOPWR0))
631 HWRITE1(hp, SDHC_POWER_CTL, 0);
637 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT) |
646 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) {
660 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq)
664 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) {
665 if (hp->clkbase <= freq)
669 if ((hp->clkbase / div) <= freq)
673 if ((hp->clkbase / div) <= freq)
688 struct sdhc_host *hp = sch;
689 struct sdhc_softc *sc = hp->sc;
698 if (hp->sc->sc_bus_clock_pre)
699 hp->sc->sc_bus_clock_pre(hp->sc, freq, timing);
703 if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK) &&
704 sdhc_card_detect(hp))
711 HWRITE2(hp, SDHC_CLOCK_CTL, 0);
717 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED);
719 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED);
722 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) {
725 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK);
726 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_DDR50);
734 if ((div = sdhc_clock_divisor(hp, freq)) < 0) {
739 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3)
743 HWRITE2(hp, SDHC_CLOCK_CTL, sdclk);
748 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE);
750 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE))
762 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE);
764 if (hp->sc->sc_bus_clock_post)
765 hp->sc->sc_bus_clock_post(hp->sc, freq, timing);
775 struct sdhc_host *hp = (struct sdhc_host *)sch;
784 reg = HREAD1(hp, SDHC_HOST_CTL);
786 if (SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3) {
792 KASSERT(SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3);
795 HWRITE1(hp, SDHC_HOST_CTL, reg);
805 struct sdhc_host *hp = sch;
808 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
809 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT);
811 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT);
812 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
819 struct sdhc_host *hp = sch;
821 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
827 struct sdhc_host *hp = sch;
829 if (hp->sc->sc_signal_voltage)
830 return hp->sc->sc_signal_voltage(hp->sc, signal_voltage);
832 if (SDHC_SPEC_VERSION(hp->version) < SDHC_SPEC_V3)
837 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN);
840 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN);
851 !ISSET(HREAD2(hp, SDHC_HOST_CTL2), SDHC_1_8V_SIGNAL_EN))
858 sdhc_wait_state(struct sdhc_host *hp, u_int32_t mask, u_int32_t value)
864 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask)
869 DPRINTF(0,("%s: timeout waiting for %x (state=%b)\n", DEVNAME(hp->sc),
877 struct sdhc_host *hp = sch;
883 error = sdhc_start_command(hp, cmd);
894 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE,
912 *p++ = HREAD1(hp, SDHC_RESPONSE + i);
914 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE);
922 sdhc_transfer_data(hp, cmd);
925 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON);
928 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_flags, cmd->c_error));
933 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd)
935 struct sdhc_adma2_descriptor32 *desc32 = (void *)hp->adma2;
936 struct sdhc_adma2_descriptor64 *desc64 = (void *)hp->adma2;
937 struct sdhc_softc *sc = hp->sc;
947 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_arg, cmd->c_data,
962 DEVNAME(hp->sc), blksize);
969 printf("%s: too much data\n", DEVNAME(hp->sc));
986 ISSET(hp->flags, SHF_USE_DMA))
1012 if ((error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0)) != 0)
1018 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON);
1021 if (cmd->c_dmamap && ISSET(hp->flags, SHF_USE_DMA)) {
1034 if (ISSET(hp->flags, SHF_USE_DMA64)) {
1048 if (ISSET(hp->flags, SHF_USE_DMA64))
1053 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE,
1056 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT);
1057 if (ISSET(hp->flags, SHF_USE_DMA64))
1058 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA64);
1060 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA32);
1062 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR,
1063 hp->adma_map->dm_segs[0].ds_addr);
1065 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT);
1068 DEVNAME(hp->sc), command, mode, blksize, blkcount));
1071 hp->intr_status = 0;
1077 HWRITE2(hp, SDHC_TRANSFER_MODE, mode);
1078 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize);
1079 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount);
1080 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg);
1081 HWRITE2(hp, SDHC_COMMAND, command);
1088 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd)
1090 struct sdhc_softc *sc = hp->sc;
1101 status = sdhc_wait_intr(hp,
1112 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE,
1122 DPRINTF(1,("%s: resp=%#x datalen=%d\n", DEVNAME(hp->sc),
1130 DEVNAME(hp->sc), MMC_R1(cmd->c_resp) & 0xff00);
1134 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY|
1140 if ((error = sdhc_wait_state(hp, mask, mask)) != 0)
1145 sdhc_read_data(hp, datap, i);
1147 sdhc_write_data(hp, datap, i);
1153 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE,
1163 DEVNAME(hp->sc), cmd->c_error));
1167 sdhc_read_data(struct sdhc_host *hp, u_char *datap, int datalen)
1170 *(u_int32_t *)datap = HREAD4(hp, SDHC_DATA);
1175 u_int32_t rv = HREAD4(hp, SDHC_DATA);
1184 sdhc_write_data(struct sdhc_host *hp, u_char *datap, int datalen)
1188 HWRITE4(hp, SDHC_DATA, *((u_int32_t *)datap));
1199 HWRITE4(hp, SDHC_DATA, rv);
1205 sdhc_soft_reset(struct sdhc_host *hp, int mask)
1209 DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(hp->sc), mask));
1211 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask);
1213 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask))
1216 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0);
1219 DPRINTF(1,("%s: timeout reg=%#x\n", DEVNAME(hp->sc),
1220 HREAD1(hp, SDHC_SOFTWARE_RESET)));
1221 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0);
1229 sdhc_wait_intr_cold(struct sdhc_host *hp, int mask, int secs)
1235 status = hp->intr_status;
1238 status = HREAD2(hp, SDHC_NINTR_STATUS);
1240 HWRITE2(hp, SDHC_NINTR_STATUS, status);
1243 error = HREAD2(hp, SDHC_EINTR_STATUS);
1244 HWRITE2(hp, SDHC_EINTR_STATUS, error);
1245 hp->intr_status |= status;
1255 hp->intr_status |= status;
1260 HSET2(hp, SDHC_NINTR_STATUS_EN,
1274 hp->intr_status &= ~(status & mask);
1279 sdhc_wait_intr(struct sdhc_host *hp, int mask, int secs)
1285 return (sdhc_wait_intr_cold(hp, mask, secs));
1290 status = hp->intr_status & mask;
1292 if (tsleep_nsec(&hp->intr_status, PWAIT, "hcintr",
1297 status = hp->intr_status & mask;
1299 hp->intr_status &= ~status;
1301 DPRINTF(2,("%s: intr status %#x error %#x\n", DEVNAME(hp->sc), status,
1302 hp->intr_error_status));
1306 hp->intr_error_status = 0;
1307 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD);
1327 struct sdhc_host *hp = sc->sc_host[host];
1330 if (hp == NULL)
1334 status = HREAD2(hp, SDHC_NINTR_STATUS);
1339 HWRITE2(hp, SDHC_NINTR_STATUS, status);
1340 DPRINTF(2,("%s: interrupt status=%b\n", DEVNAME(hp->sc),
1353 error = HREAD2(hp, SDHC_EINTR_STATUS);
1354 HWRITE2(hp, SDHC_EINTR_STATUS, error);
1356 DEVNAME(hp->sc), error, SDHC_EINTR_STATUS_BITS));
1360 hp->intr_error_status |= error;
1361 hp->intr_status |= status;
1362 wakeup(&hp->intr_status);
1370 sdmmc_needs_discover(hp->sdmmc);
1379 hp->intr_status |= status;
1380 wakeup(&hp->intr_status);
1387 DPRINTF(0,("%s: card interrupt\n", DEVNAME(hp->sc)));
1388 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
1389 sdmmc_card_intr(hp->sdmmc);
1406 sdhc_dump_regs(struct sdhc_host *hp)
1409 HREAD4(hp, SDHC_PRESENT_STATE), SDHC_PRESENT_STATE_BITS);
1411 HREAD1(hp, SDHC_POWER_CTL));
1413 HREAD2(hp, SDHC_NINTR_STATUS));
1415 HREAD2(hp, SDHC_EINTR_STATUS));
1417 HREAD2(hp, SDHC_NINTR_STATUS_EN));
1419 HREAD2(hp, SDHC_EINTR_STATUS_EN));
1421 HREAD2(hp, SDHC_NINTR_SIGNAL_EN));
1423 HREAD2(hp, SDHC_EINTR_SIGNAL_EN));
1425 HREAD4(hp, SDHC_CAPABILITIES));
1427 HREAD4(hp, SDHC_MAX_CAPABILITIES));
1434 struct sdhc_host *hp, *fhp;
1436 hp = sch;
1437 *fhp = *hp;