Lines Matching refs:samp
58 @cindex @samp{--32} option, i386
59 @cindex @samp{--32} option, x86-64
60 @cindex @samp{--x32} option, i386
61 @cindex @samp{--x32} option, x86-64
62 @cindex @samp{--64} option, i386
63 @cindex @samp{--64} option, x86-64
65 Select the word size, either 32 bits or 64 bits. @samp{--32}
66 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
81 @cindex @samp{--divide} option, i386
83 On SVR4-derived platforms, the character @samp{/} is treated as a comment
85 @samp{--divide} option turns @samp{/} into a normal character. This does
86 not disable @samp{/} at the beginning of a line starting a comment, or
87 affect using @samp{#} for starting a comment.
89 @cindex @samp{-march=} option, i386
90 @cindex @samp{-march=} option, x86-64
285 @cindex @samp{-mtune=} option, i386
286 @cindex @samp{-mtune=} option, x86-64
296 @cindex @samp{-msse2avx} option, i386
297 @cindex @samp{-msse2avx} option, x86-64
302 @cindex @samp{-muse-unaligned-vector-move} option, i386
303 @cindex @samp{-muse-unaligned-vector-move} option, x86-64
308 @cindex @samp{-msse-check=} option, i386
309 @cindex @samp{-msse-check=} option, x86-64
320 @cindex @samp{-mavxscalar=} option, i386
321 @cindex @samp{-mavxscalar=} option, x86-64
333 @cindex @samp{-mvexwig=} option, i386
334 @cindex @samp{-mvexwig=} option, x86-64
346 @cindex @samp{-mevexlig=} option, i386
347 @cindex @samp{-mevexlig=} option, x86-64
358 @cindex @samp{-mevexwig=} option, i386
359 @cindex @samp{-mevexwig=} option, x86-64
368 @cindex @samp{-mmnemonic=} option, i386
369 @cindex @samp{-mmnemonic=} option, x86-64
376 @cindex @samp{-msyntax=} option, i386
377 @cindex @samp{-msyntax=} option, x86-64
384 @cindex @samp{-mnaked-reg} option, i386
385 @cindex @samp{-mnaked-reg} option, x86-64
387 This option specifies that registers don't require a @samp{%} prefix.
390 @cindex @samp{-madd-bnd-prefix} option, i386
391 @cindex @samp{-madd-bnd-prefix} option, x86-64
396 @cindex @samp{-mshared} option, i386
397 @cindex @samp{-mshared} option, x86-64
401 The @samp{-mshared} option tells the assembler to generate code which
407 @cindex @samp{-mbig-obj} option, i386
408 @cindex @samp{-mbig-obj} option, x86-64
413 @cindex @samp{-momit-lock-prefix=} option, i386
414 @cindex @samp{-momit-lock-prefix=} option, x86-64
425 @cindex @samp{-mfence-as-lock-add=} option, i386
426 @cindex @samp{-mfence-as-lock-add=} option, x86-64
432 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
433 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
437 @cindex @samp{-mrelax-relocations=} option, i386
438 @cindex @samp{-mrelax-relocations=} option, x86-64
449 @cindex @samp{-malign-branch-boundary=} option, i386
450 @cindex @samp{-malign-branch-boundary=} option, x86-64
458 @cindex @samp{-malign-branch=} option, i386
459 @cindex @samp{-malign-branch=} option, x86-64
462 combination of @samp{jcc}, which aligns conditional jumps,
463 @samp{fused}, which aligns fused conditional jumps, @samp{jmp},
464 which aligns unconditional jumps, @samp{call} which aligns calls,
465 @samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect
468 @cindex @samp{-malign-branch-prefix-size=} option, i386
469 @cindex @samp{-malign-branch-prefix-size=} option, x86-64
475 @cindex @samp{-mbranches-within-32B-boundaries} option, i386
476 @cindex @samp{-mbranches-within-32B-boundaries} option, x86-64
486 @cindex @samp{-mlfence-after-load=} option, i386
487 @cindex @samp{-mlfence-after-load=} option, x86-64
495 @cindex @samp{-mlfence-before-indirect-branch=} option, i386
496 @cindex @samp{-mlfence-before-indirect-branch=} option, x86-64
518 @cindex @samp{-mlfence-before-ret=} option, i386
519 @cindex @samp{-mlfence-before-ret=} option, x86-64
533 @cindex @samp{-mx86-used-note=} option, i386
534 @cindex @samp{-mx86-used-note=} option, x86-64
542 @cindex @samp{-mevexrcig=} option, i386
543 @cindex @samp{-mevexrcig=} option, x86-64
555 @cindex @samp{-mamd64} option, x86-64
556 @cindex @samp{-mintel64} option, x86-64
563 @cindex @samp{-O0} option, i386
564 @cindex @samp{-O0} option, x86-64
565 @cindex @samp{-O} option, i386
566 @cindex @samp{-O} option, x86-64
567 @cindex @samp{-O1} option, i386
568 @cindex @samp{-O1} option, x86-64
569 @cindex @samp{-O2} option, i386
570 @cindex @samp{-O2} option, x86-64
571 @cindex @samp{-Os} option, i386
572 @cindex @samp{-Os} option, x86-64
574 Optimize instruction encoding with smaller instruction size. @samp{-O}
575 and @samp{-O1} encode 64-bit register load instructions with 64-bit
585 @samp{-O2} includes @samp{-O1} optimization plus encodes
593 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
595 immediate. @samp{-O0} turns off this optimization.
720 @samp{%cl} in shift/rotate instructions have to be omitted, or else
760 specified. In Intel syntax @samp{DWORD PTR} and alike can be used to
764 @samp{8(%eax)@{1to8:d8@}}.
798 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
820 AT&T immediate operands are preceded by @samp{$}; Intel immediate
821 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
822 AT&T register operands are preceded by @samp{%}; Intel register operands
824 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
832 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
833 @samp{source, dest} convention is maintained for compatibility with
834 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
835 instructions with 2 immediate operands, such as the @samp{enter}
846 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
847 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
849 of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm
853 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr},
854 @samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel
855 syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
856 syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and
857 @samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references.
859 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
868 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
870 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
872 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
873 @samp{ret far @var{stack-adjust}}.
889 The presence of a @samp{#} appearing anywhere on a line indicates the
892 If a @samp{#} appears as the first character of a line then the whole
898 then the @samp{/} character appearing anywhere on a line also
904 The @samp{;} character can be used to separate statements on the same
917 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
918 and @samp{q} specify byte, word, long and quadruple word operands. If
921 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
922 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
923 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
960 @samp{@{disp8@}} -- prefer 8-bit displacement.
963 @samp{@{disp32@}} -- prefer 32-bit displacement.
966 @samp{@{disp16@}} -- prefer 16-bit displacement.
969 @samp{@{load@}} -- prefer load-form instruction.
972 @samp{@{store@}} -- prefer store-form instruction.
975 @samp{@{vex@}} -- encode with VEX prefix.
978 @samp{@{vex3@}} -- encode with 3-byte VEX prefix.
981 @samp{@{evex@}} -- encode with EVEX prefix.
984 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
985 instructions (x86-64 only). Note that this differs from the @samp{rex}
989 @samp{@{rex2@}} -- prefer REX2 prefix for integer and legacy vector
993 @samp{@{nooptimize@}} -- disable instruction size optimization.
997 by default. The pseudo @samp{@{vex@}} prefix can be used to encode
1008 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
1011 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
1014 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
1017 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
1020 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
1024 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
1025 @samp{%rdx:%rax} (x86-64 only),
1029 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
1030 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
1041 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg16}.
1044 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg32}.
1047 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg64}
1051 @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg32}
1054 @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg64}
1058 @samp{movsxd} --- sign-extend @samp{reg32/mem32} to @samp{reg64}
1062 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg16}.
1065 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg32}.
1068 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg64}
1072 @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg32}
1075 @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg64}
1080 are called @samp{movsbw/movsxb/movsx}, @samp{movsbl/movsxb/movsx},
1081 @samp{movsbq/movsxb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw},
1082 @samp{movslq/movsxl}, @samp{movzbw/movzxb/movzx},
1083 @samp{movzbl/movzxb/movzx}, @samp{movzbq/movzxb/movzx},
1084 @samp{movzwl/movzxw} and @samp{movzwq/movzxw} in AT&T syntax.
1090 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
1091 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
1103 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
1104 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
1105 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
1110 @item @samp{movslq} with AT&T mnemonic only accepts 64-bit destination
1111 register. @samp{movsxd} should be used to encode 16-bit or 32-bit
1122 Register operands are always prefixed with @samp{%}. The 80386 registers
1127 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
1128 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
1129 frame pointer), and @samp{%esp} (the stack pointer).
1132 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
1133 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
1136 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
1137 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
1138 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
1139 @samp{%cx}, and @samp{%dx})
1142 the 6 section registers @samp{%cs} (code section), @samp{%ds}
1143 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
1144 and @samp{%gs}.
1147 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
1148 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
1151 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
1152 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
1155 the 2 test registers @samp{%tr6} and @samp{%tr7}.
1158 the 8 floating point register stack @samp{%st} or equivalently
1159 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
1160 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
1161 These registers are overloaded by 8 MMX registers @samp{%mm0},
1162 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
1163 @samp{%mm6} and @samp{%mm7}.
1166 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
1167 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
1174 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
1175 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
1176 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
1180 the 8 extended registers @samp{%r8}--@samp{%r15}.
1183 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
1186 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
1189 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
1192 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
1195 the 8 debug registers: @samp{%db8}--@samp{%db15}.
1198 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
1206 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
1208 @samp{xmm0}--@samp{xmm15} registers.
1217 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
1219 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
1220 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
1223 the 8 mask registers @samp{%k0}--@samp{%k7}.
1239 they act upon. For example, the @samp{scas} (scan string) instruction is
1255 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
1256 @samp{fs}, @samp{gs}. These are automatically added by specifying
1261 Operand/Address size prefixes @samp{data16} and @samp{addr16}
1263 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
1276 The bus lock prefix @samp{lock} inhibits interrupts during execution of
1282 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
1288 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
1289 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
1293 The @samp{rex} family of prefixes is used by x86-64 to encode
1294 extensions to i386 instruction set. The @samp{rex} prefix has four
1299 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
1300 instruction emits @samp{rex} prefix with all the bits set. By omitting
1336 be preceded by a @samp{%}. If you specify a section override which
1345 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
1346 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
1347 missing, and the default section is used (@samp{%ss} for addressing with
1348 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
1350 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
1351 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
1352 @samp{foo}. All other fields are missing. The section register here
1353 defaults to @samp{%ds}.
1355 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
1356 This uses the value pointed to by @samp{foo} as a memory operand.
1358 @emph{one} @samp{,}. This is a syntactic exception.
1360 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
1361 This selects the contents of the variable @samp{foo} with section
1362 register @var{section} being @samp{%gs}.
1366 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
1371 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1375 addressing. This addressing mode is specified by using @samp{rip} as a
1379 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1383 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1403 instruction with the @samp{data16} instruction prefix), since the 80386
1404 insists upon masking @samp{%eip} to 16 bits after the word displacement
1407 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1408 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1411 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1450 Floating point constructors are @samp{.float} or @samp{.single},
1451 @samp{.double}, @samp{.tfloat}, @samp{.hfloat}, and @samp{.bfloat16} for 32-,
1453 correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, and @samp{t}.
1454 @samp{t} stands for 80-bit (ten byte) real. The 80387 only supports this
1455 format via the @samp{fldt} (load 80-bit real to stack top) and @samp{fstpt}
1467 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1468 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1469 corresponding instruction mnemonic suffixes are @samp{s} (short),
1470 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1471 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1472 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1477 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1478 wrote @samp{fst %st, %st(1)}, since all register to register operations
1479 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1480 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1481 then stores the result in the 4 byte location @samp{mem})
1503 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1504 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1575 mode code segments. To do this, put a @samp{.code16} or
1576 @samp{.code16gcc} directive before the assembly language instructions to
1578 32-bit code with the @samp{.code32} directive or 64-bit code with the
1579 @samp{.code64} directive.
1581 @samp{.code16gcc} provides experimental support for generating 16-bit
1582 code from gcc, and differs from @samp{.code16} in that @samp{call},
1583 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1584 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1588 @samp{.code16gcc} also automatically adds address size prefixes where
1601 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1602 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1609 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1627 @item @samp{default} @tab @samp{push} @tab @samp{pop}
1628 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1629 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1630 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1631 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1632 @item @samp{corei7} @tab @samp{iamcu}
1633 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1634 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1635 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3}
1636 @item @samp{znver4} @tab @samp{znver5} @tab @samp{btver1} @tab @samp{btver2}
1637 @item @samp{generic32}
1638 @item @samp{generic64} @tab @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
1639 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
1640 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1641 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1642 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1643 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1644 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1645 @item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc}
1646 @item @samp{.monitor} @tab @samp{.hle} @tab @samp{.rtm} @tab @samp{.tsx}
1647 @item @samp{.lahf_sahf} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1648 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1649 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1650 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1651 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1652 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1653 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1654 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
1655 @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @tab @samp{.avx10.1}
1656 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
1657 @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
1658 @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
1659 @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
1660 @item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4}
1661 @item @samp{.pbndkb} @tab @samp{.user_msr}
1662 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1663 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1664 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
1665 @item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_fp16}
1666 @item @samp{.amx_complex} @tab @samp{.amx_tile}
1667 @item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset}
1668 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1669 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
1670 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1671 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
1672 @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb}
1673 @item @samp{.tlbsync} @tab @samp{.apx_f}
1678 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1682 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1683 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1684 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1691 Note further that @samp{.avx10.<N>} can be suffixed with a vector length
1692 restriction (@samp{/256} or @samp{/128}, with @samp{/512} simply restoring the
1695 On SVR4-derived platforms, the separator character @samp{/} can be replaced by
1696 @samp{:}.
1699 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1700 control automatic promotion of conditional jumps. @samp{jumps} is the
1703 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1706 Unconditional jumps are treated as for @samp{jumps}.
1720 @item For @samp{movsxd} with 16-bit destination register, AMD64
1726 operand size, encoded as @samp{ljmpq} and @samp{lcallq} in AT&T syntax
1727 and with an explicit @samp{tbyte ptr} operand size specifier in Intel
1730 @item @samp{lfs}, @samp{lgs}, and @samp{lss} similarly allow for 16-
1752 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1753 than the expected @samp{%st(3) - %st}. This happens with all the
1755 operands where the source register is @samp{%st} and the destination
1756 register is @samp{%st(i)}.
1766 There is some trickery concerning the @samp{mul} and @samp{imul}
1768 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1769 for @samp{imul}) can be output only in the one operand form. Thus,
1770 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1771 the expanding multiply would clobber the @samp{%edx} register, and this
1772 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1773 64-bit product in @samp{%edx:%eax}.
1775 We have added a two operand form of @samp{imul} when the first operand
1777 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1778 example, can be done with @samp{imul $69, %eax} rather than @samp{imul