Lines Matching refs:code
49 Specify which ABI the source code uses. The recognized arguments
50 are: @code{ilp32} and @code{lp64}, which decides the generated object
51 file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
58 @code{cortex-a34},
59 @code{cortex-a35},
60 @code{cortex-a53},
61 @code{cortex-a55},
62 @code{cortex-a57},
63 @code{cortex-a65},
64 @code{cortex-a65ae},
65 @code{cortex-a72},
66 @code{cortex-a73},
67 @code{cortex-a75},
68 @code{cortex-a76},
69 @code{cortex-a76ae},
70 @code{cortex-a77},
71 @code{cortex-a78},
72 @code{cortex-a78ae},
73 @code{cortex-a78c},
74 @code{cortex-a510},
75 @code{cortex-a520},
76 @code{cortex-a710},
77 @code{cortex-a720},
78 @code{ares},
79 @code{exynos-m1},
80 @code{falkor},
81 @code{neoverse-n1},
82 @code{neoverse-n2},
83 @code{neoverse-e1},
84 @code{neoverse-v1},
85 @code{qdf24xx},
86 @code{saphira},
87 @code{thunderx},
88 @code{vulcan},
89 @code{xgene1}
90 @code{xgene2},
91 @code{cortex-r82},
92 @code{cortex-x1},
93 @code{cortex-x2},
94 @code{cortex-x3},
96 @code{cortex-x4}.
97 The special name @code{all} may be used to allow the assembler to accept
115 following architecture names are recognized: @code{armv8-a},
116 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
117 @code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8.8-a},
118 @code{armv8.9-a}, @code{armv8-r}, @code{armv9-a}, @code{armv9.1-a},
119 @code{armv9.2-a}, @code{armv9.3-a} and @code{armv9.4-a}.
130 @cindex @code{-mverbose-error} command-line option, AArch64
135 @cindex @code{-mno-verbose-error} command-line option, AArch64
149 Multiple extensions may be specified, separated by a @code{+}.
151 accepts. This is done by prepending @code{no} to the option that adds
162 @item @code{aes} @tab @code{simd}
164 @item @code{b16b16} @tab @code{sve2}
166 @item @code{bf16} @tab @code{fp}
168 @item @code{chk} @tab
170 @item @code{compnum} @tab @code{simd}
171 @tab Enable the complex number SIMD extensions. An alias of @code{fcma}.
172 @item @code{crc} @tab
174 @item @code{crypto} @tab @code{simd}
175 @tab Enable cryptographic extensions. This is equivalent to @code{aes+sha2}.
176 @item @code{cssc} @tab
178 @item @code{d128} @tab @code{lse128}
179 @tab Enable the 128-bit Page Descriptor Extension. This implies @code{lse128}.
180 @item @code{dotprod} @tab @code{simd}
182 @item @code{f32mm} @tab @code{sve}
184 @item @code{f64mm} @tab @code{sve}
186 @item @code{fcma} @tab @code{fp16}, @code{simd}
188 @item @code{flagm} @tab
190 @item @code{flagm2} @tab @code{flagm}
192 @item @code{fp16fml} @tab @code{fp16}
194 @item @code{fp16} @tab @code{fp}
196 @item @code{fp} @tab
198 @item @code{frintts} @tab @code{simd}
200 @item @code{gcs} @tab
202 @item @code{hbc} @tab
204 @item @code{i8mm} @tab @code{simd}
206 @item @code{ite} @tab
208 @item @code{jscvt} @tab @code{fp}
209 @tab Enable the @code{fjcvtzs} JavaScript conversion instruction.
210 @item @code{lor} @tab
212 @item @code{ls64} @tab
214 @item @code{lse} @tab
216 @item @code{lse128} @tab @code{lse}
218 @item @code{memtag} @tab
220 @item @code{mops} @tab
222 @item @code{pan} @tab
224 @item @code{pauth} @tab
226 @item @code{predres} @tab
228 @item @code{predres2} @tab @code{predres}
230 @item @code{profile} @tab
232 @item @code{ras} @tab
234 @item @code{rasv2} @tab @code{ras}
236 @item @code{rcpc} @tab
238 @item @code{rcpc2} @tab @code{rcpc}
240 @item @code{rcpc3} @tab @code{rcpc2}
242 @item @code{rdma} @tab @code{simd}
244 @item @code{rdm} @tab @code{simd}
245 @tab An alias of @code{rdma}.
246 @item @code{rng} @tab
248 @item @code{sb} @tab
250 @item @code{sha2} @tab @code{simd}
252 @item @code{sha3} @tab @code{sha2}
254 @item @code{simd} @tab @code{fp}
256 @item @code{sm4} @tab @code{simd}
258 @item @code{sme} @tab @code{sve2}, @code{bf16}
260 @item @code{sme-f64f64} @tab @code{sme}
262 @item @code{sme-i16i64} @tab @code{sme}
264 @item @code{sme2} @tab @code{sme}
266 @item @code{sme2p1} @tab @code{sme2}
268 @item @code{ssbs} @tab
270 @item @code{sve} @tab @code{fcma}
272 @item @code{sve2} @tab @code{sve}
274 @item @code{sve2-aes} @tab @code{sve2}, @code{aes}
276 @item @code{sve2-bitperm} @tab @code{sve2}
278 @item @code{sve2-sha3} @tab @code{sve2}, @code{sha3}
280 @item @code{sve2-sm4} @tab @code{sve2}, @code{sm4}
282 @item @code{sve2p1} @tab @code{sve2}
284 @item @code{the} @tab
286 @item @code{tme} @tab
288 @item @code{wfxt} @tab
289 @tab Enable @code{wfet} and @code{wfit} instructions.
290 @item @code{xs} @tab
296 @item @code{armv8-a} @tab @code{simd}, @code{chk}, @code{ras}
297 @item @code{armv8.1-a} @tab @code{armv8-a}, @code{crc}, @code{lse}, @code{rdma}, @code{pan}, @code{…
298 @item @code{armv8.2-a} @tab @code{armv8.1-a}
299 @item @code{armv8.3-a} @tab @code{armv8.2-a}, @code{fcma}, @code{jscvt}, @code{pauth}, @code{rcpc}
300 @item @code{armv8.4-a} @tab @code{armv8.3-a}, @code{fp16fml}, @code{dotprod}, @code{flagm}, @code{r…
301 @item @code{armv8.5-a} @tab @code{armv8.4-a}, @code{frintts}, @code{flagm2}, @code{predres}, @code{…
302 @item @code{armv8.6-a} @tab @code{armv8.5-a}, @code{bf16}, @code{i8mm}
303 @item @code{armv8.7-a} @tab @code{armv8.6-a}, @code{ls64}, @code{xs}, @code{wfxt}
304 @item @code{armv8.8-a} @tab @code{armv8.7-a}, @code{hbc}, @code{mops}
305 @item @code{armv8.9-a} @tab @code{armv8.8-a}, @code{rasv2}, @code{predres2}
306 @item @code{armv9-a} @tab @code{armv8.5-a}, @code{sve2}
307 @item @code{armv9.1-a} @tab @code{armv9-a}, @code{armv8.6-a}
308 @item @code{armv9.2-a} @tab @code{armv9.1-a}, @code{armv8.7-a}
309 @item @code{armv9.3-a} @tab @code{armv9.2-a}, @code{armv8.8-a}
310 @item @code{armv9.4-a} @tab @code{armv9.3-a}, @code{armv8.9-a}
311 @item @code{armv8-r} @tab @code{armv8.4-a+nolor}
410 @table @code
414 @cindex @code{.arch} directive, AArch64
419 Specifying @code{.arch} clears any previously selected architecture
422 @cindex @code{.arch_extension} directive, AArch64
428 @code{.arch_extension} may be used multiple times to add or remove extensions
434 @cindex @code{.cpu} directive, AArch64
441 @cindex @code{.dword} directive, AArch64
443 The @code{.dword} directive produces 64 bit values.
447 @cindex @code{.even} directive, AArch64
449 The @code{.even} directive aligns the output on the next even byte
454 @cindex @code{.float16} directive, AArch64
465 @cindex @code{.inst} directive, AArch64
474 @cindex @code{.ltorg} directive, AArch64
480 sub-section. The @code{.ltorg} directive will only affect the literal
495 @cindex @code{.pool} directive, AArch64
502 @cindex @code{.req} directive, AArch64
518 @cindex @code{.tlsdescadd} directive, AArch64
519 @item @code{.tlsdescadd}
522 @cindex @code{.tlsdesccall} directive, AArch64
523 @item @code{.tlsdesccall}
526 @cindex @code{.tlsdescldr} directive, AArch64
527 @item @code{.tlsdescldr}
532 @cindex @code{.unreq} directive, AArch64
535 @code{req} directive. For example:
548 @cindex @code{.variant_pcs} directive, AArch64
557 @cindex @code{.xword} directive, AArch64
559 The @code{.xword} directive produces 64 bit values. This is the same
560 as the @code{.dword} directive.
565 @cindex @code{.cfi_b_key_frame} directive, AArch64
566 @item @code{.cfi_b_key_frame}
567 The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
584 @table @code
586 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
608 @table @code
610 @cindex @code{$x}
612 At the start of a region of code containing AArch64 instructions.
614 @cindex @code{$d}