Lines Matching full:lowering

21 lowering paths.
66 2.  `Virtual Vector -> Hardware Vector` lowering is specified as a set of MLIR
67     lowering patterns that are specified manually for now.
68 3.  `Hardware Vector -> LLVM` lowering is a mechanical process that is written
85 The section on [LLVM Lowering Tradeoffs](#llvm-lowering-tradeoffs) offers a
110 cost-based lowering decisions in MLIR even for `LLVM`. Specialized `CPU`
164 2.  The lowering of `vector_transfer` ops legalizes `vector` load/store ops to
173 ### Virtual Vector to Hardware Vector Lowering
178 [VectorOuterProductOp lowering](https://github.com/tensorflow/mlir/commit/957b1ca9680b4aacabb3a480fbc4ebd2506334b8)).
242 lowering. The argument can be made that automatic vectorization on a loops + ops
281 ## LLVM Lowering Tradeoffs
283 This section describes the tradeoffs involved in lowering the MLIR n-D vector
297 ### Alternatives For Lowering an n-D Vector Type to LLVM
300 `vector<s_0x...s_{n-1}xf32>`). Lowering such an `n-D` MLIR vector type to an
305     lowering in MLIR).
351 flattened lowering of an MLIR n-D vector to an LLVM 1-D vector.
447 Alternatively, we argue that directly lowering to a linearized abstraction hides
463 #### Implication on Lowering to Accelerators
468 appropriate constant. Then, the existing lowering to LLVM-IR immediately
472 the figure above) to lower the `vector.cast`. Accelerator -> LLVM lowering would
500 higher level of abstraction and allows the lowering of generic operations on
521 lowering from MLIR because: