Lines Matching +full:2 +full:- +full:d
2 ; RUN: llc -mtriple=aarch64 -mattr=+sve < %s -o - | FileCheck --check-prefix=SVE %s
3 ; RUN: llc -mtriple=aarch64 -mattr=+sve2 < %s -o - | FileCheck --check-prefix=SVE2 %s
5 … 16 x i8> @eor3_nxv16i8_left(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2) {
6 ; SVE-LABEL: eor3_nxv16i8_left:
8 ; SVE-NEXT: eor z0.d, z0.d, z1.d
9 ; SVE-NEXT: eor z0.d, z0.d, z2.d
10 ; SVE-NEXT: ret
12 ; SVE2-LABEL: eor3_nxv16i8_left:
14 ; SVE2-NEXT: eor3 z0.d, z0.d, z1.d, z2.d
15 ; SVE2-NEXT: ret
17 %5 = xor <vscale x 16 x i8> %4, %2
21 …16 x i8> @eor3_nxv16i8_right(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2) {
22 ; SVE-LABEL: eor3_nxv16i8_right:
24 ; SVE-NEXT: eor z0.d, z0.d, z1.d
25 ; SVE-NEXT: eor z0.d, z2.d, z0.d
26 ; SVE-NEXT: ret
28 ; SVE2-LABEL: eor3_nxv16i8_right:
30 ; SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z1.d
31 ; SVE2-NEXT: mov z0.d, z2.d
32 ; SVE2-NEXT: ret
34 %5 = xor <vscale x 16 x i8> %2, %4
38 … 8 x i16> @eor3_nxv8i16_left(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2) {
39 ; SVE-LABEL: eor3_nxv8i16_left:
41 ; SVE-NEXT: eor z0.d, z0.d, z1.d
42 ; SVE-NEXT: eor z0.d, z0.d, z2.d
43 ; SVE-NEXT: ret
45 ; SVE2-LABEL: eor3_nxv8i16_left:
47 ; SVE2-NEXT: eor3 z0.d, z0.d, z1.d, z2.d
48 ; SVE2-NEXT: ret
50 %5 = xor <vscale x 8 x i16> %4, %2
54 …8 x i16> @eor3_nxv8i16_right(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2) {
55 ; SVE-LABEL: eor3_nxv8i16_right:
57 ; SVE-NEXT: eor z0.d, z0.d, z1.d
58 ; SVE-NEXT: eor z0.d, z2.d, z0.d
59 ; SVE-NEXT: ret
61 ; SVE2-LABEL: eor3_nxv8i16_right:
63 ; SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z1.d
64 ; SVE2-NEXT: mov z0.d, z2.d
65 ; SVE2-NEXT: ret
67 %5 = xor <vscale x 8 x i16> %2, %4
71 … 4 x i32> @eor3_nxv4i32_left(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2) {
72 ; SVE-LABEL: eor3_nxv4i32_left:
74 ; SVE-NEXT: eor z0.d, z0.d, z1.d
75 ; SVE-NEXT: eor z0.d, z0.d, z2.d
76 ; SVE-NEXT: ret
78 ; SVE2-LABEL: eor3_nxv4i32_left:
80 ; SVE2-NEXT: eor3 z0.d, z0.d, z1.d, z2.d
81 ; SVE2-NEXT: ret
83 %5 = xor <vscale x 4 x i32> %4, %2
87 …4 x i32> @eor3_nxv4i32_right(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2) {
88 ; SVE-LABEL: eor3_nxv4i32_right:
90 ; SVE-NEXT: eor z0.d, z0.d, z1.d
91 ; SVE-NEXT: eor z0.d, z2.d, z0.d
92 ; SVE-NEXT: ret
94 ; SVE2-LABEL: eor3_nxv4i32_right:
96 ; SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z1.d
97 ; SVE2-NEXT: mov z0.d, z2.d
98 ; SVE2-NEXT: ret
100 %5 = xor <vscale x 4 x i32> %2, %4
104 define <vscale x 2 x i64> @eor3_nxv2i64_left(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale …
105 ; SVE-LABEL: eor3_nxv2i64_left:
107 ; SVE-NEXT: eor z0.d, z0.d, z1.d
108 ; SVE-NEXT: eor z0.d, z0.d, z2.d
109 ; SVE-NEXT: ret
111 ; SVE2-LABEL: eor3_nxv2i64_left:
113 ; SVE2-NEXT: eor3 z0.d, z0.d, z1.d, z2.d
114 ; SVE2-NEXT: ret
115 %4 = xor <vscale x 2 x i64> %0, %1
116 %5 = xor <vscale x 2 x i64> %4, %2
117 ret <vscale x 2 x i64> %5
120 define <vscale x 2 x i64> @eor3_nxv2i64_right(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale…
121 ; SVE-LABEL: eor3_nxv2i64_right:
123 ; SVE-NEXT: eor z0.d, z0.d, z1.d
124 ; SVE-NEXT: eor z0.d, z2.d, z0.d
125 ; SVE-NEXT: ret
127 ; SVE2-LABEL: eor3_nxv2i64_right:
129 ; SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z1.d
130 ; SVE2-NEXT: mov z0.d, z2.d
131 ; SVE2-NEXT: ret
132 %4 = xor <vscale x 2 x i64> %0, %1
133 %5 = xor <vscale x 2 x i64> %2, %4
134 ret <vscale x 2 x i64> %5
137 define <vscale x 2 x i64> @eor3_vnot(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1) {
138 ; SVE-LABEL: eor3_vnot:
140 ; SVE-NEXT: eor z0.d, z0.d, z1.d
141 ; SVE-NEXT: ret
143 ; SVE2-LABEL: eor3_vnot:
145 ; SVE2-NEXT: eor z0.d, z0.d, z1.d
146 ; SVE2-NEXT: ret
147 %3 = xor <vscale x 2 x i64> %0, zeroinitializer
148 %4 = xor <vscale x 2 x i64> %3, %1
149 ret <vscale x 2 x i64> %4