Lines Matching full:right
6 ; Check that an expanded vbsl(vneg(pre_cond), left, right) lowers to a VBSL
14 define <4 x i32> @vbsl_neg_cond_0000(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
23 %right_bits_0 = and <4 x i32> %min_cond, %right
28 define <4 x i32> @vbsl_neg_cond_0001(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
37 %right_bits_0 = and <4 x i32> %min_cond, %right
42 define <4 x i32> @vbsl_neg_cond_0010(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
51 %right_bits_1 = and <4 x i32> %right, %min_cond
56 define <4 x i32> @vbsl_neg_cond_0011(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
65 %right_bits_1 = and <4 x i32> %right, %min_cond
70 define <4 x i32> @vbsl_neg_cond_0100(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
79 %right_bits_0 = and <4 x i32> %min_cond, %right
84 define <4 x i32> @vbsl_neg_cond_0101(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
93 %right_bits_1 = and <4 x i32> %right, %min_cond
98 define <4 x i32> @vbsl_neg_cond_0110(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
107 %right_bits_0 = and <4 x i32> %min_cond, %right
112 define <4 x i32> @vbsl_neg_cond_0111(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
121 %right_bits_1 = and <4 x i32> %right, %min_cond
126 define <4 x i32> @vbsl_neg_cond_1000(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
135 %flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right
140 define <4 x i32> @vbsl_neg_cond_1001(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
149 %flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right
154 define <4 x i32> @vbsl_neg_cond_1010(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
163 %flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond
168 define <4 x i32> @vbsl_neg_cond_1011(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
177 %flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond
182 define <4 x i32> @vbsl_neg_cond_1100(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
191 %flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right
196 define <4 x i32> @vbsl_neg_cond_1101(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
205 %flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond
210 define <4 x i32> @vbsl_neg_cond_1110(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
219 %flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right
224 define <4 x i32> @vbsl_neg_cond_1111(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
233 %flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond