Lines Matching full:left
6 ; Check that an expanded vbsl(vneg(pre_cond), left, right) lowers to a VBSL
14 define <4 x i32> @vbsl_neg_cond_0000(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
22 %left_bits_0 = and <4 x i32> %neg_cond, %left
28 define <4 x i32> @vbsl_neg_cond_0001(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
36 %left_bits_1 = and <4 x i32> %left, %neg_cond
42 define <4 x i32> @vbsl_neg_cond_0010(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
50 %left_bits_0 = and <4 x i32> %neg_cond, %left
56 define <4 x i32> @vbsl_neg_cond_0011(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
64 %left_bits_1 = and <4 x i32> %left, %neg_cond
70 define <4 x i32> @vbsl_neg_cond_0100(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
78 %left_bits_0 = and <4 x i32> %neg_cond, %left
84 define <4 x i32> @vbsl_neg_cond_0101(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
92 %left_bits_0 = and <4 x i32> %neg_cond, %left
98 define <4 x i32> @vbsl_neg_cond_0110(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
106 %left_bits_1 = and <4 x i32> %left, %neg_cond
112 define <4 x i32> @vbsl_neg_cond_0111(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
120 %left_bits_1 = and <4 x i32> %left, %neg_cond
126 define <4 x i32> @vbsl_neg_cond_1000(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
134 %flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left
140 define <4 x i32> @vbsl_neg_cond_1001(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
148 %flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond
154 define <4 x i32> @vbsl_neg_cond_1010(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
162 %flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left
168 define <4 x i32> @vbsl_neg_cond_1011(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
176 %flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond
182 define <4 x i32> @vbsl_neg_cond_1100(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
190 %flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left
196 define <4 x i32> @vbsl_neg_cond_1101(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
204 %flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left
210 define <4 x i32> @vbsl_neg_cond_1110(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
218 %flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond
224 define <4 x i32> @vbsl_neg_cond_1111(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {
232 %flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond