Lines Matching defs:BitShift

4931                                   SDValue &AlignedAddr, SDValue &BitShift,
4942   BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
4944   BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
4949                             DAG.getConstant(0, DL, WideVT), BitShift);
4981   SDValue AlignedAddr, BitShift, NegBitShift;
4982   getCSAddressAndShifts(Addr, DAG, DL, AlignedAddr, BitShift, NegBitShift);
4999   SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
5006   SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
5077   SDValue AlignedAddr, BitShift, NegBitShift;
5078   getCSAddressAndShifts(Addr, DAG, DL, AlignedAddr, BitShift, NegBitShift);
5082   SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
9018   Register BitShift = MI.getOperand(4).getReg();
9050   //   %RotatedOldVal = RLL %OldVal, 0(%BitShift)
9061     .addReg(OldVal).addReg(BitShift).addImm(0);
9113   Register BitShift = MI.getOperand(4).getReg();
9148   //   %RotatedOldVal = RLL %OldVal, 0(%BitShift)
9156     .addReg(OldVal).addReg(BitShift).addImm(0);
9215   Register BitShift = MI.getOperand(5).getReg();
9257   //   %OldValRot     = RLL %OldVal, BitSize(%BitShift)
9275     .addReg(OldVal).addReg(BitShift).addImm(BitSize);