Lines Matching defs:Reg2

438                     Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
1007 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
1009                                     bool &HaveReg2, Register &Reg2,
1036   // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
1084         if (parseIntegerRegister(Reg2, RegGR))
1088           if (parseRegister(Reg2, /*RequirePercent=*/true))
1092           Reg2.Num = 0;
1093           Reg2.Group = RegGR;
1094           Reg2.StartLoc = Reg2.EndLoc = Parser.getTok().getLoc();
1128   Register Reg1, Reg2;
1135   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1154     // There must be no Reg2.
1176     // If we have Reg2, it must be an address register.
1178       if (parseAddressRegister(Reg2))
1180       Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
1184     // If we have Reg2, it must be an address register.
1186       if (parseAddressRegister(Reg2))
1188       Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
1202     // If we have Reg2, it must be an address register.
1204       if (parseAddressRegister(Reg2))
1206       Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
1214     // In GAS mode, we must have Reg2, since a single register would be
1218     // If we have Reg2, it must be an address register.
1220       if (parseAddressRegister(Reg2))
1222       Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
1538   Register Reg1, Reg2;
1542   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1550   if (HaveReg2 && parseAddressRegister(Reg2))