Lines Matching defs:MemKind

117   // MemKind says what type of memory this is and RegKind says what type
123     unsigned MemKind : 4;
190   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
194     Op->Mem.MemKind = MemKind;
199     if (MemKind == BDLMem)
201     if (MemKind == BDRMem)
262   bool isMem(MemoryKind MemKind) const {
264             (Mem.MemKind == MemKind ||
267              (Mem.MemKind == BDMem && MemKind == BDXMem)));
269   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
270     return isMem(MemKind) && Mem.RegKind == RegKind;
272   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
273     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff, true);
275   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
276     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287, true);
446   ParseStatus parseAddress(OperandVector &Operands, MemoryKind MemKind,
755       if (Op.MemKind == BDLMem)
757       else if (Op.MemKind == BDRMem)
1124                                            MemoryKind MemKind,
1133   bool HasLength = (MemKind == BDLMem) ? true : false;
1134   bool HasVectorIndex = (MemKind == BDVMem) ? true : false;
1146   switch (MemKind) {
1163       if (MemKind == LXAMem)
1229   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,