Lines Matching defs:EndLoc

94   SMLoc StartLoc, EndLoc;
158   SystemZOperand(OperandKind Kind, SMLoc StartLoc, SMLoc EndLoc)
159       : Kind(Kind), StartLoc(StartLoc), EndLoc(EndLoc) {}
163                                                        SMLoc EndLoc) {
164     return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
175   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
176     auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
183   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
184     auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
192             unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
193     auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
208                SMLoc StartLoc, SMLoc EndLoc) {
209     auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
292   SMLoc getEndLoc() const override { return EndLoc; }
297   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
418     SMLoc StartLoc, EndLoc;
506   bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
507   bool ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
510                                SMLoc &EndLoc) override;
827   Reg.EndLoc = Parser.getTok().getLoc();
910       SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
930     SMLoc EndLoc =
933     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
974                                                  Reg.StartLoc, Reg.EndLoc));
1001   Reg.EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1094           Reg2.StartLoc = Reg2.EndLoc = Parser.getTok().getLoc();
1227   SMLoc EndLoc =
1231                                                StartLoc, EndLoc));
1313       SMLoc EndLoc =
1316       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1398                                      SMLoc &EndLoc, bool RequirePercent,
1414   EndLoc = Reg.EndLoc;
1419                                      SMLoc &EndLoc) {
1420   return ParseRegister(Reg, StartLoc, EndLoc, /*RequirePercent=*/false,
1425                                                SMLoc &EndLoc) {
1426   bool Result = ParseRegister(Reg, StartLoc, EndLoc, /*RequirePercent=*/false,
1530     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1553   SMLoc EndLoc =
1556     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1558     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1695   SMLoc EndLoc =
1700                                                     StartLoc, EndLoc));
1702     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));