Lines Matching defs:Disp
116 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
125 const MCExpr *Disp;
191 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
198 Op->Mem.Disp = Disp;
273 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff, true);
276 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287, true);
313 addExpr(Inst, Mem.Disp);
319 addExpr(Inst, Mem.Disp);
326 addExpr(Inst, Mem.Disp);
333 addExpr(Inst, Mem.Disp);
340 addExpr(Inst, Mem.Disp);
347 addExpr(Inst, Mem.Disp);
438 Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
752 OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
1007 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
1010 const MCExpr *&Disp, const MCExpr *&Length,
1013 if (getParser().parseExpression(Disp))
1130 const MCExpr *Disp;
1135 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1229 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,