Lines Matching defs:ResVReg
106 bool spvSelect(Register ResVReg, const SPIRVType *ResType,
109 bool selectFirstBitHigh(Register ResVReg, const SPIRVType *ResType,
112 bool selectFirstBitLow(Register ResVReg, const SPIRVType *ResType,
115 bool selectFirstBitSet16(Register ResVReg, const SPIRVType *ResType,
119 bool selectFirstBitSet32(Register ResVReg, const SPIRVType *ResType,
123 bool selectFirstBitSet64(Register ResVReg, const SPIRVType *ResType,
127 bool selectFirstBitSet64Overflow(Register ResVReg, const SPIRVType *ResType,
132 bool selectGlobalValue(Register ResVReg, MachineInstr &I,
135 bool selectOpWithSrcs(Register ResVReg, const SPIRVType *ResType,
139 bool selectUnOp(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
142 bool selectBitcast(Register ResVReg, const SPIRVType *ResType,
145 bool selectLoad(Register ResVReg, const SPIRVType *ResType,
149 bool selectStackSave(Register ResVReg, const SPIRVType *ResType,
153 bool selectMemOperation(Register ResVReg, MachineInstr &I) const;
155 bool selectAtomicRMW(Register ResVReg, const SPIRVType *ResType,
159 bool selectAtomicCmpXchg(Register ResVReg, const SPIRVType *ResType,
164 bool selectAddrSpaceCast(Register ResVReg, const SPIRVType *ResType,
167 bool selectAnyOrAll(Register ResVReg, const SPIRVType *ResType,
170 bool selectAll(Register ResVReg, const SPIRVType *ResType,
173 bool selectAny(Register ResVReg, const SPIRVType *ResType,
176 bool selectBitreverse(Register ResVReg, const SPIRVType *ResType,
179 bool selectBuildVector(Register ResVReg, const SPIRVType *ResType,
181 bool selectSplatVector(Register ResVReg, const SPIRVType *ResType,
184 bool selectCmp(Register ResVReg, const SPIRVType *ResType,
186 bool selectCross(Register ResVReg, const SPIRVType *ResType,
188 bool selectDiscard(Register ResVReg, const SPIRVType *ResType,
191 bool selectICmp(Register ResVReg, const SPIRVType *ResType,
193 bool selectFCmp(Register ResVReg, const SPIRVType *ResType,
196 bool selectSign(Register ResVReg, const SPIRVType *ResType,
199 bool selectFloatDot(Register ResVReg, const SPIRVType *ResType,
202 bool selectOverflowArith(Register ResVReg, const SPIRVType *ResType,
205 bool selectIntegerDot(Register ResVReg, const SPIRVType *ResType,
208 bool selectIntegerDotExpansion(Register ResVReg, const SPIRVType *ResType,
212 bool selectDot4AddPacked(Register ResVReg, const SPIRVType *ResType,
215 bool selectDot4AddPackedExpansion(Register ResVReg, const SPIRVType *ResType,
218 bool selectWaveReduceMax(Register ResVReg, const SPIRVType *ResType,
221 bool selectWaveReduceSum(Register ResVReg, const SPIRVType *ResType,
229 bool selectConst(Register ResVReg, const SPIRVType *ResType, const APInt &Imm,
232 bool selectSelect(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
234 bool selectIToF(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
236 bool selectExt(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
239 bool selectTrunc(Register ResVReg, const SPIRVType *ResType,
242 bool selectSUCmp(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
245 bool selectIntToBool(Register IntReg, Register ResVReg, MachineInstr &I,
248 bool selectOpUndef(Register ResVReg, const SPIRVType *ResType,
250 bool selectFreeze(Register ResVReg, const SPIRVType *ResType,
252 bool selectIntrinsic(Register ResVReg, const SPIRVType *ResType,
254 bool selectExtractVal(Register ResVReg, const SPIRVType *ResType,
256 bool selectInsertVal(Register ResVReg, const SPIRVType *ResType,
258 bool selectExtractElt(Register ResVReg, const SPIRVType *ResType,
260 bool selectInsertElt(Register ResVReg, const SPIRVType *ResType,
262 bool selectGEP(Register ResVReg, const SPIRVType *ResType,
265 bool selectFrameIndex(Register ResVReg, const SPIRVType *ResType,
267 bool selectAllocaArray(Register ResVReg, const SPIRVType *ResType,
273 bool selectPhi(Register ResVReg, const SPIRVType *ResType,
276 [[maybe_unused]] bool selectExtInst(Register ResVReg,
280 bool selectExtInst(Register ResVReg, const SPIRVType *ResType,
282 bool selectExtInst(Register ResVReg, const SPIRVType *ResType,
285 bool selectExtInst(Register ResVReg, const SPIRVType *ResType,
288 bool selectLog10(Register ResVReg, const SPIRVType *ResType,
291 bool selectSaturate(Register ResVReg, const SPIRVType *ResType,
294 bool selectWaveOpInst(Register ResVReg, const SPIRVType *ResType,
297 bool selectWaveActiveCountBits(Register ResVReg, const SPIRVType *ResType,
302 bool selectHandleFromBinding(Register &ResVReg, const SPIRVType *ResType,
305 bool selectReadImageIntrinsic(Register &ResVReg, const SPIRVType *ResType,
308 bool selectResourceGetPointer(Register &ResVReg, const SPIRVType *ResType,
337 bool extractSubvector(Register &ResVReg, const SPIRVType *ResType,
339 bool generateImageRead(Register &ResVReg, const SPIRVType *ResType,
344 Register ResVReg, const SPIRVType *ResType,
496 Register ResVReg = HasDefs ? I.getOperand(0).getReg() : Register(0);
497 SPIRVType *ResType = HasDefs ? GR.getSPIRVTypeForVReg(ResVReg) : nullptr;
499 if (spvSelect(ResVReg, ResType, I)) {
534 bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
542 return selectConst(ResVReg, ResType, I.getOperand(1).getCImm()->getValue(),
545 return selectGlobalValue(ResVReg, I);
547 return selectOpUndef(ResVReg, ResType, I);
549 return selectFreeze(ResVReg, ResType, I);
555 return selectIntrinsic(ResVReg, ResType, I);
557 return selectBitreverse(ResVReg, ResType, I);
560 return selectBuildVector(ResVReg, ResType, I);
562 return selectSplatVector(ResVReg, ResType, I);
567 .addDef(ResVReg)
578 return selectMemOperation(ResVReg, I);
581 return selectICmp(ResVReg, ResType, I);
583 return selectFCmp(ResVReg, ResType, I);
586 return selectFrameIndex(ResVReg, ResType, I);
589 return selectLoad(ResVReg, ResType, I);
599 return selectPhi(ResVReg, ResType, I);
602 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToS);
604 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToU);
607 return selectIToF(ResVReg, ResType, I, true, SPIRV::OpConvertSToF);
609 return selectIToF(ResVReg, ResType, I, false, SPIRV::OpConvertUToF);
612 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitCount);
614 return selectExtInst(ResVReg, ResType, I, CL::s_min, GL::SMin);
616 return selectExtInst(ResVReg, ResType, I, CL::u_min, GL::UMin);
619 return selectExtInst(ResVReg, ResType, I, CL::s_max, GL::SMax);
621 return selectExtInst(ResVReg, ResType, I, CL::u_max, GL::UMax);
624 return selectSUCmp(ResVReg, ResType, I, true);
626 return selectSUCmp(ResVReg, ResType, I, false);
630 return selectExtInst(ResVReg, ResType, I, CL::fma, GL::Fma);
633 return selectExtInst(ResVReg, ResType, I, CL::ldexp);
636 return selectExtInst(ResVReg, ResType, I, CL::pow, GL::Pow);
638 return selectExtInst(ResVReg, ResType, I, CL::pown);
641 return selectExtInst(ResVReg, ResType, I, CL::exp, GL::Exp);
643 return selectExtInst(ResVReg, ResType, I, CL::exp2, GL::Exp2);
646 return selectExtInst(ResVReg, ResType, I, CL::log, GL::Log);
648 return selectExtInst(ResVReg, ResType, I, CL::log2, GL::Log2);
650 return selectLog10(ResVReg, ResType, I);
653 return selectExtInst(ResVReg, ResType, I, CL::fabs, GL::FAbs);
655 return selectExtInst(ResVReg, ResType, I, CL::s_abs, GL::SAbs);
659 return selectExtInst(ResVReg, ResType, I, CL::fmin, GL::NMin);
662 return selectExtInst(ResVReg, ResType, I, CL::fmax, GL::NMax);
665 return selectExtInst(ResVReg, ResType, I, CL::copysign);
668 return selectExtInst(ResVReg, ResType, I, CL::ceil, GL::Ceil);
670 return selectExtInst(ResVReg, ResType, I, CL::floor, GL::Floor);
673 return selectExtInst(ResVReg, ResType, I, CL::cos, GL::Cos);
675 return selectExtInst(ResVReg, ResType, I, CL::sin, GL::Sin);
677 return selectExtInst(ResVReg, ResType, I, CL::tan, GL::Tan);
679 return selectExtInst(ResVReg, ResType, I, CL::acos, GL::Acos);
681 return selectExtInst(ResVReg, ResType, I, CL::asin, GL::Asin);
683 return selectExtInst(ResVReg, ResType, I, CL::atan, GL::Atan);
685 return selectExtInst(ResVReg, ResType, I, CL::atan2, GL::Atan2);
687 return selectExtInst(ResVReg, ResType, I, CL::cosh, GL::Cosh);
689 return selectExtInst(ResVReg, ResType, I, CL::sinh, GL::Sinh);
691 return selectExtInst(ResVReg, ResType, I, CL::tanh, GL::Tanh);
695 return selectExtInst(ResVReg, ResType, I, CL::sqrt, GL::Sqrt);
699 return selectExtInst(ResVReg, ResType, I, CL::ctz);
702 return selectExtInst(ResVReg, ResType, I, CL::clz);
705 return selectExtInst(ResVReg, ResType, I, CL::round, GL::Round);
707 return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven);
709 return selectExtInst(ResVReg, ResType, I, CL::trunc, GL::Trunc);
712 return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven);
715 return selectExtInst(ResVReg, ResType, I, CL::s_mul_hi);
717 return selectExtInst(ResVReg, ResType, I, CL::u_mul_hi);
720 return selectExtInst(ResVReg, ResType, I, CL::s_add_sat);
722 return selectExtInst(ResVReg, ResType, I, CL::u_add_sat);
724 return selectExtInst(ResVReg, ResType, I, CL::s_sub_sat);
726 return selectExtInst(ResVReg, ResType, I, CL::u_sub_sat);
729 return selectOverflowArith(ResVReg, ResType, I,
734 return selectOverflowArith(ResVReg, ResType, I,
739 return selectOverflowArith(ResVReg, ResType, I, SPIRV::OpUMulExtended);
741 return selectOverflowArith(ResVReg, ResType, I, SPIRV::OpSMulExtended);
744 return selectExt(ResVReg, ResType, I, true);
747 return selectExt(ResVReg, ResType, I, false);
749 return selectTrunc(ResVReg, ResType, I);
752 return selectUnOp(ResVReg, ResType, I, SPIRV::OpFConvert);
755 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertPtrToU);
757 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertUToPtr);
759 return selectBitcast(ResVReg, ResType, I);
761 return selectAddrSpaceCast(ResVReg, ResType, I);
814 .addDef(ResVReg)
821 .addDef(ResVReg)
835 .addDef(ResVReg)
846 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicOr);
848 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicIAdd);
850 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicAnd);
852 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicSMax);
854 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicSMin);
856 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicISub);
858 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicXor);
860 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicUMax);
862 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicUMin);
864 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicExchange);
866 return selectAtomicCmpXchg(ResVReg, ResType, I);
869 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFAddEXT);
872 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFAddEXT,
875 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFMinEXT);
877 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFMaxEXT);
883 return selectStackSave(ResVReg, ResType, I);
904 bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
908 return selectExtInst(ResVReg, ResType, I,
912 bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
916 return selectExtInst(ResVReg, ResType, I,
920 bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
927 return selectExtInst(ResVReg, ResType, I, ExtInsts);
930 bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
941 .addDef(ResVReg)
959 bool SPIRVInstructionSelector::selectOpWithSrcs(Register ResVReg,
965 .addDef(ResVReg)
973 bool SPIRVInstructionSelector::selectUnOp(Register ResVReg,
1001 .addDef(ResVReg)
1008 return selectOpWithSrcs(ResVReg, ResType, I, {I.getOperand(1).getReg()},
1012 bool SPIRVInstructionSelector::selectBitcast(Register ResVReg,
1019 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitcast);
1050 bool SPIRVInstructionSelector::selectLoad(Register ResVReg,
1070 return generateImageRead(ResVReg, ResType, NewImageReg, IdxReg,
1075 .addDef(ResVReg)
1131 bool SPIRVInstructionSelector::selectStackSave(Register ResVReg,
1141 .addDef(ResVReg)
1160 bool SPIRVInstructionSelector::selectMemOperation(Register ResVReg,
1206 if (ResVReg.isValid() && ResVReg != MIB->getOperand(0).getReg())
1207 Result &= BuildCOPY(ResVReg, MIB->getOperand(0).getReg(), I);
1211 bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg,
1245 .addDef(ResVReg)
1269 Register ResVReg = I.getOperand(i).getReg();
1270 SPIRVType *ResType = GR.getSPIRVTypeForVReg(ResVReg);
1274 MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
1275 MRI->setType(ResVReg, LLT::scalar(GR.getScalarOrVectorBitWidth(ResType)));
1276 GR.assignSPIRVTypeToVReg(ResType, ResVReg, *GR.CurMF);
1280 .addDef(ResVReg)
1309 bool SPIRVInstructionSelector::selectOverflowArith(Register ResVReg,
1373 bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg,
1446 .addDef(ResVReg)
1475 // Returns true ResVReg is referred only from global vars and OpName's.
1476 static bool isASCastInGVar(MachineRegisterInfo *MRI, Register ResVReg) {
1479 std::all_of(MRI->use_instr_begin(ResVReg), MRI->use_instr_end(),
1532 bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg,
1544 return BuildCOPY(ResVReg, SrcPtr, I);
1549 if (isASCastInGVar(MRI, ResVReg)) {
1566 return buildSpecConstantOp(I, ResVReg, SrcPtr,
1573 I, ResVReg, MIB->getOperand(0).getReg(),
1582 return BuildCOPY(ResVReg, SrcPtr, I);
1588 return BuildCOPY(ResVReg, SrcPtr, I);
1592 return selectUnOp(ResVReg, ResType, I, SPIRV::OpPtrCastToGeneric);
1595 return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr);
1607 .addDef(ResVReg)
1616 return selectUnOp(ResVReg, ResType, I,
1619 return selectUnOp(ResVReg, ResType, I,
1622 return selectUnOp(ResVReg, ResType, I, SPIRV::OpPtrCastToGeneric);
1624 return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr);
1746 bool SPIRVInstructionSelector::selectAnyOrAll(Register ResVReg,
1762 assert(ResVReg == I.getOperand(0).getReg());
1763 return BuildCOPY(ResVReg, InputRegister, I);
1771 Register NotEqualReg = ResVReg;
1797 .addDef(ResVReg)
1803 bool SPIRVInstructionSelector::selectAll(Register ResVReg,
1806 return selectAnyOrAll(ResVReg, ResType, I, SPIRV::OpAll);
1809 bool SPIRVInstructionSelector::selectAny(Register ResVReg,
1812 return selectAnyOrAll(ResVReg, ResType, I, SPIRV::OpAny);
1816 bool SPIRVInstructionSelector::selectFloatDot(Register ResVReg,
1837 .addDef(ResVReg)
1844 bool SPIRVInstructionSelector::selectIntegerDot(Register ResVReg,
1855 .addDef(ResVReg)
1865 Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const {
1909 : ResVReg;
1924 bool SPIRVInstructionSelector::selectDot4AddPacked(Register ResVReg,
1943 .addDef(ResVReg)
1955 Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const {
2013 i < 3 ? MRI->createVirtualRegister(&SPIRV::IDRegClass) : ResVReg;
2029 bool SPIRVInstructionSelector::selectSaturate(Register ResVReg,
2039 .addDef(ResVReg)
2049 bool SPIRVInstructionSelector::selectSign(Register ResVReg,
2072 : ResVReg;
2086 .addDef(ResVReg)
2095 bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg,
2103 .addDef(ResVReg)
2116 Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const {
2128 .addDef(ResVReg)
2138 bool SPIRVInstructionSelector::selectWaveReduceMax(Register ResVReg,
2158 .addDef(ResVReg)
2166 bool SPIRVInstructionSelector::selectWaveReduceSum(Register ResVReg,
2184 .addDef(ResVReg)
2191 bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg,
2196 .addDef(ResVReg)
2202 bool SPIRVInstructionSelector::selectFreeze(Register ResVReg,
2307 bool SPIRVInstructionSelector::selectBuildVector(Register ResVReg,
2331 MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
2335 .addDef(ResVReg)
2342 bool SPIRVInstructionSelector::selectSplatVector(Register ResVReg,
2365 MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
2369 .addDef(ResVReg)
2376 bool SPIRVInstructionSelector::selectDiscard(Register ResVReg,
2400 bool SPIRVInstructionSelector::selectCmp(Register ResVReg,
2410 .addDef(ResVReg)
2417 bool SPIRVInstructionSelector::selectICmp(Register ResVReg,
2430 return selectCmp(ResVReg, ResType, CmpOpc, I);
2480 bool SPIRVInstructionSelector::selectFCmp(Register ResVReg,
2484 return selectCmp(ResVReg, ResType, CmpOp, I);
2527 bool SPIRVInstructionSelector::selectSelect(Register ResVReg,
2539 .addDef(ResVReg)
2547 bool SPIRVInstructionSelector::selectIToF(Register ResVReg,
2564 return selectOpWithSrcs(ResVReg, ResType, I, {SrcReg}, Opcode);
2567 bool SPIRVInstructionSelector::selectExt(Register ResVReg,
2572 return selectSelect(ResVReg, ResType, I, IsSigned);
2576 return BuildCOPY(ResVReg, SrcReg, I);
2579 return selectUnOp(ResVReg, ResType, I, Opcode);
2582 bool SPIRVInstructionSelector::selectSUCmp(Register ResVReg,
2635 .addDef(ResVReg)
2644 Register ResVReg,
2662 .addDef(ResVReg)
2669 bool SPIRVInstructionSelector::selectTrunc(Register ResVReg,
2674 if (GR.isScalarOrVectorOfType(ResVReg, SPIRV::OpTypeBool))
2675 return selectIntToBool(IntReg, ResVReg, I, ArgType, ResType);
2677 return BuildCOPY(ResVReg, IntReg, I);
2680 return selectUnOp(ResVReg, ResType, I, Opcode);
2683 bool SPIRVInstructionSelector::selectConst(Register ResVReg,
2693 .addDef(ResVReg)
2699 return Reg == ResVReg ? true : BuildCOPY(ResVReg, Reg, I);
2702 .addDef(ResVReg)
2710 bool SPIRVInstructionSelector::selectOpUndef(Register ResVReg,
2714 .addDef(ResVReg)
2739 bool SPIRVInstructionSelector::selectInsertVal(Register ResVReg,
2744 .addDef(ResVReg)
2755 bool SPIRVInstructionSelector::selectExtractVal(Register ResVReg,
2760 .addDef(ResVReg)
2768 bool SPIRVInstructionSelector::selectInsertElt(Register ResVReg,
2772 return selectInsertVal(ResVReg, ResType, I);
2775 .addDef(ResVReg)
2783 bool SPIRVInstructionSelector::selectExtractElt(Register ResVReg,
2787 return selectExtractVal(ResVReg, ResType, I);
2790 .addDef(ResVReg)
2797 bool SPIRVInstructionSelector::selectGEP(Register ResVReg,
2812 .addDef(ResVReg)
2870 bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
2877 return selectLoad(ResVReg, ResType, I);
2881 return selectExtractVal(ResVReg, ResType, I);
2883 return selectInsertVal(ResVReg, ResType, I);
2885 return selectExtractElt(ResVReg, ResType, I);
2887 return selectInsertElt(ResVReg, ResType, I);
2889 return selectGEP(ResVReg, ResType, I);
2901 .addDef(ResVReg)
2916 MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
2918 .addDef(ResVReg)
2969 return selectAtomicCmpXchg(ResVReg, ResType, I);
2974 return selectFrameIndex(ResVReg, ResType, I);
2976 return selectAllocaArray(ResVReg, ResType, I);
2986 .addDef(ResVReg)
2996 .addDef(ResVReg)
3001 return BuildCOPY(ResVReg, I.getOperand(2).getReg(), I);
3009 return loadVec3BuiltinInputID(SPIRV::BuiltIn::GlobalInvocationId, ResVReg,
3017 return loadVec3BuiltinInputID(SPIRV::BuiltIn::LocalInvocationId, ResVReg,
3025 return loadVec3BuiltinInputID(SPIRV::BuiltIn::WorkgroupId, ResVReg, ResType,
3028 return selectFloatDot(ResVReg, ResType, I);
3033 return selectIntegerDot(ResVReg, ResType, I,
3035 return selectIntegerDotExpansion(ResVReg, ResType, I);
3039 return selectDot4AddPacked<true>(ResVReg, ResType, I);
3040 return selectDot4AddPackedExpansion<true>(ResVReg, ResType, I);
3044 return selectDot4AddPacked<false>(ResVReg, ResType, I);
3045 return selectDot4AddPackedExpansion<false>(ResVReg, ResType, I);
3047 return selectAll(ResVReg, ResType, I);
3049 return selectAny(ResVReg, ResType, I);
3051 return selectExtInst(ResVReg, ResType, I, CL::cross, GL::Cross);
3053 return selectExtInst(ResVReg, ResType, I, CL::distance, GL::Distance);
3055 return selectExtInst(ResVReg, ResType, I, CL::mix, GL::FMix);
3057 return selectExtInst(ResVReg, ResType, I, CL::length, GL::Length);
3059 return selectExtInst(ResVReg, ResType, I, CL::degrees, GL::Degrees);
3061 return selectExtInst(ResVReg, ResType, I, CL::fract, GL::Fract);
3063 return selectExtInst(ResVReg, ResType, I, CL::normalize, GL::Normalize);
3065 return selectExtInst(ResVReg, ResType, I, CL::rsqrt, GL::InverseSqrt);
3067 return selectSign(ResVReg, ResType, I);
3069 return selectFirstBitHigh(ResVReg, ResType, I, /*IsSigned=*/false);
3071 return selectFirstBitHigh(ResVReg, ResType, I, /*IsSigned=*/true);
3073 return selectFirstBitLow(ResVReg, ResType, I);
3105 return selectSaturate(ResVReg, ResType, I);
3107 return selectExtInst(ResVReg, ResType, I, CL::fclamp, GL::NClamp);
3109 return selectExtInst(ResVReg, ResType, I, CL::u_clamp, GL::UClamp);
3111 return selectExtInst(ResVReg, ResType, I, CL::s_clamp, GL::SClamp);
3113 return selectWaveActiveCountBits(ResVReg, ResType, I);
3115 return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAll);
3117 return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAny);
3119 return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformElect);
3121 return selectWaveReduceMax(ResVReg, ResType, I, /*IsUnsigned*/ true);
3123 return selectWaveReduceMax(ResVReg, ResType, I, /*IsUnsigned*/ false);
3125 return selectWaveReduceSum(ResVReg, ResType, I);
3127 return selectWaveOpInst(ResVReg, ResType, I,
3130 return selectExtInst(ResVReg, ResType, I, CL::step, GL::Step);
3132 return selectExtInst(ResVReg, ResType, I, CL::radians, GL::Radians);
3144 return selectHandleFromBinding(ResVReg, ResType, I);
3150 return selectReadImageIntrinsic(ResVReg, ResType, I);
3153 return selectResourceGetPointer(ResVReg, ResType, I);
3156 return selectDiscard(ResVReg, ResType, I);
3169 bool SPIRVInstructionSelector::selectHandleFromBinding(Register &ResVReg,
3176 Register &ResVReg, const SPIRVType *ResType, MachineInstr &I) const {
3196 return generateImageRead(ResVReg, ResType, NewImageReg, IdxReg, Loc, Pos);
3199 bool SPIRVInstructionSelector::generateImageRead(Register &ResVReg,
3207 .addDef(ResVReg)
3229 .addDef(ResVReg)
3235 return extractSubvector(ResVReg, ResType, ReadReg, Pos);
3239 Register &ResVReg, const SPIRVType *ResType, MachineInstr &I) const {
3257 Register &ResVReg, const SPIRVType *ResType, Register &ReadReg,
3288 .addDef(ResVReg)
3358 Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
3365 selectFirstBitSet32(ResVReg, ResType, I, ExtReg, BitSetOpcode);
3369 Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
3372 .addDef(ResVReg)
3381 Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
3453 return selectOpWithSrcs(ResVReg, ResType, I, PartialRegs,
3458 Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
3473 return selectFirstBitSet64Overflow(ResVReg, ResType, I, SrcReg,
3599 return selectOpWithSrcs(ResVReg, ResType, I, {ValReg, TmpReg}, AddOp);
3602 bool SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
3615 return selectFirstBitSet16(ResVReg, ResType, I, ExtendOpcode, BitSetOpcode);
3617 return selectFirstBitSet32(ResVReg, ResType, I, OpReg, BitSetOpcode);
3619 return selectFirstBitSet64(ResVReg, ResType, I, OpReg, BitSetOpcode,
3627 bool SPIRVInstructionSelector::selectFirstBitLow(Register ResVReg,
3641 return selectFirstBitSet16(ResVReg, ResType, I, ExtendOpcode, BitSetOpcode);
3643 return selectFirstBitSet32(ResVReg, ResType, I, OpReg, BitSetOpcode);
3645 return selectFirstBitSet64(ResVReg, ResType, I, OpReg, BitSetOpcode,
3652 bool SPIRVInstructionSelector::selectAllocaArray(Register ResVReg,
3660 .addDef(ResVReg)
3666 buildOpDecorate(ResVReg, I, TII, SPIRV::Decoration::Alignment, {Alignment});
3671 bool SPIRVInstructionSelector::selectFrameIndex(Register ResVReg,
3679 .addDef(ResVReg)
3685 buildOpDecorate(ResVReg, *It, TII, SPIRV::Decoration::Alignment,
3737 bool SPIRVInstructionSelector::selectPhi(Register ResVReg,
3741 .addDef(ResVReg)
3755 Register ResVReg, MachineInstr &I, const MachineInstr *Init) const {
3797 Register NewReg = ResVReg;
3836 assert(NewReg != ResVReg);
3837 return BuildCOPY(ResVReg, NewReg, I);
3862 ResVReg, ResType, GlobalIdent, GV, StorageClass, Init,
3867 bool SPIRVInstructionSelector::selectLog10(Register ResVReg,
3871 return selectExtInst(ResVReg, ResType, I, CL::log10);
3909 .addDef(ResVReg)
3920 SPIRV::BuiltIn::BuiltIn BuiltInValue, Register ResVReg,
3963 .addDef(ResVReg)