Lines Matching full:pseudo

10 // RISC-V GlobalISel target pseudo instruction definitions. This is kept
20 // Pseudo equivalent to a RISCVISD::SRAW.
28 // Pseudo equivalent to a RISCVISD::SRLW.
36 // Pseudo equivalent to a RISCVISD::SLLW.
44 // Pseudo equivalent to a RISCVISD::DIVW.
52 // Pseudo equivalent to a RISCVISD::DIVUW.
60 // Pseudo equivalent to a RISCVISD::REMUW.
68 // Pseudo equivalent to a RISCVISD::RORW.
76 // Pseudo equivalent to a RISCVISD::ROLW.
84 // Pseudo equivalent to a RISCVISD::CLZW.
92 // Pseudo equivalent to a RISCVISD::CTZW.
100 // Pseudo equivalent to a RISCVISD::FCVT_W_RV64.
108 // Pseudo equivalent to a RISCVISD::FCVT_WU_RV64.
116 // Pseudo equivalent to a RISCVISD::FCLASS.
124 // Pseudo equivalent to a RISCVISD::READ_VLENB.
132 // Pseudo equivalent to a RISCVISD::VMCLR_VL
140 // Pseudo equivalent to a RISCVISD::VMSET_VL
148 // Pseudo equivalent to a RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL. There is no
157 // Pseudo equivalent to a RISCVISD::VSLIDEDOWN_VL
166 // Pseudo equivalent to a RISCVISD::VMV_V_V_VL
174 // Pseudo equivalent to a RISCVISD::VSLIDEUP_VL