Lines Matching defs:MIB
69 void preISelLower(MachineInstr &MI, MachineIRBuilder &MIB);
71 bool replacePtrWithInt(MachineOperand &Op, MachineIRBuilder &MIB);
75 bool selectImplicitDef(MachineInstr &MI, MachineIRBuilder &MIB) const;
76 bool materializeImm(Register Reg, int64_t Imm, MachineIRBuilder &MIB) const;
77 bool selectAddr(MachineInstr &MI, MachineIRBuilder &MIB, bool IsLocal = true,
79 bool selectSelect(MachineInstr &MI, MachineIRBuilder &MIB) const;
80 bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB) const;
82 MachineIRBuilder &MIB) const;
83 bool selectUnmergeValues(MachineInstr &MI, MachineIRBuilder &MIB) const;
123 void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
125 void renderImmSubFromXLen(MachineInstrBuilder &MIB, const MachineInstr &MI,
127 void renderImmSubFrom32(MachineInstrBuilder &MIB, const MachineInstr &MI,
129 void renderImmPlus1(MachineInstrBuilder &MIB, const MachineInstr &MI,
131 void renderImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
133 void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
136 void renderTrailingZeros(MachineInstrBuilder &MIB, const MachineInstr &MI,
138 void renderXLenSubTrailingOnes(MachineInstrBuilder &MIB,
141 void renderAddiPairImmLarge(MachineInstrBuilder &MIB, const MachineInstr &MI,
143 void renderAddiPairImmSmall(MachineInstrBuilder &MIB, const MachineInstr &MI,
245 return {{[=](MachineInstrBuilder &MIB) {
246 MachineIRBuilder(*MIB.getInstr())
248 MIB.addReg(ShAmtReg);
255 return {{[=](MachineInstrBuilder &MIB) {
256 MachineIRBuilder(*MIB.getInstr())
259 MIB.addReg(ShAmtReg);
264 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(ShAmtReg); }}};
278 {[=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); }}};
283 return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
298 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(RegX); }}};
303 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(RegX); }}};
307 return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
347 return {{[=](MachineInstrBuilder &MIB) {
348 MachineIRBuilder(*MIB.getInstr())
351 MIB.addReg(DstReg);
359 return {{[=](MachineInstrBuilder &MIB) {
360 MachineIRBuilder(*MIB.getInstr())
363 MIB.addReg(DstReg);
398 return {{[=](MachineInstrBuilder &MIB) {
399 MachineIRBuilder(*MIB.getInstr())
402 MIB.addReg(DstReg);
435 return {{[=](MachineInstrBuilder &MIB) {
436 MachineIRBuilder(*MIB.getInstr())
439 MIB.addReg(DstReg);
459 return {{[=](MachineInstrBuilder &MIB) {
460 MIB.addImm(RISCV::VLMaxSentinel);
465 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(ZExtC); }}};
468 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }}};
479 [=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); },
480 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); },
494 [=](MachineInstrBuilder &MIB) { MIB.add(LHSDef->getOperand(1)); },
495 [=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC); },
498 return {{[=](MachineInstrBuilder &MIB) { MIB.add(LHS); },
499 [=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC); }}};
505 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },
506 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }}};
595 MachineIRBuilder MIB(MI);
597 preISelLower(MI, MIB);
649 if (!materializeImm(DstReg, Imm, MIB))
664 if (!materializeImm(GPRReg, Imm.getSExtValue(), MIB))
670 auto FMV = MIB.buildInstr(Opcode, {DstReg}, {GPRReg});
680 MIB))
682 if (!materializeImm(GPRRegLow, Imm.trunc(32).getSExtValue(), MIB))
684 MachineInstrBuilder PairF64 = MIB.buildInstr(
700 return selectAddr(MI, MIB, GV->isDSOLocal(), GV->hasExternalWeakLinkage());
704 return selectAddr(MI, MIB, MRI);
710 auto Bcc = MIB.buildInstr(RISCVCC::getBrCond(CC), {}, {LHS, RHS})
720 return selectSelect(MI, MIB);
722 return selectFPCompare(MI, MIB);
728 emitFence(FenceOrdering, FenceSSID, MIB);
733 return selectImplicitDef(MI, MIB);
735 return selectUnmergeValues(MI, MIB);
742 MachineInstr &MI, MachineIRBuilder &MIB) const {
757 MachineInstr *ExtractLo = MIB.buildInstr(RISCV::FMV_X_W_FPR64, {Lo}, {Src});
761 MachineInstr *ExtractHi = MIB.buildInstr(RISCV::FMVH_X_D, {Hi}, {Src});
770 MachineIRBuilder &MIB) {
775 auto PtrToInt = MIB.buildPtrToInt(sXLen, PtrReg);
782 MachineIRBuilder &MIB) {
788 replacePtrWithInt(MI.getOperand(1), MIB);
796 replacePtrWithInt(MI.getOperand(1), MIB);
804 void RISCVInstructionSelector::renderNegImm(MachineInstrBuilder &MIB,
810 MIB.addImm(-CstVal);
813 void RISCVInstructionSelector::renderImmSubFromXLen(MachineInstrBuilder &MIB,
819 MIB.addImm(STI.getXLen() - CstVal);
822 void RISCVInstructionSelector::renderImmSubFrom32(MachineInstrBuilder &MIB,
828 MIB.addImm(32 - CstVal);
831 void RISCVInstructionSelector::renderImmPlus1(MachineInstrBuilder &MIB,
837 MIB.addImm(CstVal + 1);
840 void RISCVInstructionSelector::renderImm(MachineInstrBuilder &MIB,
846 MIB.addImm(CstVal);
849 void RISCVInstructionSelector::renderFrameIndex(MachineInstrBuilder &MIB,
854 MIB.add(MI.getOperand(1));
857 void RISCVInstructionSelector::renderTrailingZeros(MachineInstrBuilder &MIB,
863 MIB.addImm(llvm::countr_zero(C));
867 MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
871 MIB.addImm(Subtarget->getXLen() - llvm::countr_one(C));
874 void RISCVInstructionSelector::renderAddiPairImmSmall(MachineInstrBuilder &MIB,
881 MIB.addImm(Imm - Adj);
884 void RISCVInstructionSelector::renderAddiPairImmLarge(MachineInstrBuilder &MIB,
890 MIB.addImm(Imm);
959 MachineIRBuilder &MIB) const {
978 MachineIRBuilder &MIB) const {
980 MIB.buildCopy(DstReg, Register(RISCV::X0));
999 Result = MIB.buildInstr(I.getOpcode(), {TmpReg}, {})
1004 Result = MIB.buildInstr(I.getOpcode(), {TmpReg},
1008 Result = MIB.buildInstr(I.getOpcode(), {TmpReg}, {SrcReg, SrcReg});
1012 MIB.buildInstr(I.getOpcode(), {TmpReg}, {SrcReg}).addImm(I.getImm());
1026 MachineIRBuilder &MIB, bool IsLocal,
1062 auto Result = MIB.buildInstr(RISCV::PseudoLGA, {DefReg}, {})
1084 MachineInstr *AddrHi = MIB.buildInstr(RISCV::LUI, {AddrHiDest}, {})
1090 auto Result = MIB.buildInstr(RISCV::ADDI, {DefReg}, {AddrHiDest})
1116 auto Result = MIB.buildInstr(RISCV::PseudoLGA, {DefReg}, {})
1138 MachineIRBuilder &MIB) const {
1154 MachineInstr *Result = MIB.buildInstr(Opc)
1218 MachineIRBuilder &MIB) const {
1236 auto Cmp = MIB.buildInstr(getFCmpOpcode(Pred, Size), {TmpReg}, {LHS, RHS});
1242 auto Cmp1 = MIB.buildInstr(getFCmpOpcode(CmpInst::FCMP_OLT, Size),
1246 auto Cmp2 = MIB.buildInstr(getFCmpOpcode(CmpInst::FCMP_OLT, Size),
1253 MIB.buildInstr(RISCV::OR, {TmpReg}, {Cmp1.getReg(0), Cmp2.getReg(0)});
1260 auto Cmp1 = MIB.buildInstr(getFCmpOpcode(CmpInst::FCMP_OEQ, Size),
1264 auto Cmp2 = MIB.buildInstr(getFCmpOpcode(CmpInst::FCMP_OEQ, Size),
1271 MIB.buildInstr(RISCV::AND, {TmpReg}, {Cmp1.getReg(0), Cmp2.getReg(0)});
1279 auto Xor = MIB.buildInstr(RISCV::XORI, {DstReg}, {TmpReg}).addImm(1);
1290 MachineIRBuilder &MIB) const {
1297 MIB.buildInstr(RISCV::FENCE, {}, {})
1304 MIB.buildInstr(TargetOpcode::MEMBARRIER, {}, {});
1312 MIB.buildInstr(TargetOpcode::MEMBARRIER, {}, {});
1324 MIB.buildInstr(RISCV::FENCE_TSO, {}, {});
1342 MIB.buildInstr(RISCV::FENCE, {}, {}).addImm(Pred).addImm(Succ);