Lines Matching defs:ShiftBits

979     // rlwinm rA, rA, ShiftBits, 0, 31.
1024     unsigned ShiftBits = getEncodingValue(DestReg)*4;
1025     // rlwinm r11, r11, 32-ShiftBits, 0, 31.
1027              .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
1138     // rlwinm rA, rA, ShiftBits, 0, 0.
1186   unsigned ShiftBits = getEncodingValue(DestReg);
1187   // rlwimi r11, r10, 32-ShiftBits, ..., ...
1191       .addImm(ShiftBits ? 32 - ShiftBits : 0)
1192       .addImm(ShiftBits)
1193       .addImm(ShiftBits);