Lines Matching defs:SrcReg

180   bool emitStore(MVT VT, unsigned SrcReg, Address &Addr);
181   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
182   bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
185   bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
187   bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
188   bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
190   bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
213   MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
215     return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
804 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr) {
834     emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
845         .addReg(SrcReg)
914   unsigned SrcReg = 0;
931   SrcReg = getRegForValue(Op0);
932   if (SrcReg == 0)
940   if (!emitStore(VT, SrcReg, Addr))
1009   Register SrcReg =
1012   if (!SrcReg)
1016   emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
1088   Register SrcReg = getRegForValue(Src);
1089   if (!SrcReg)
1096   emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1124   Register SrcReg = getRegForValue(Src);
1125   if (SrcReg == 0)
1135   emitInst(Opc, TempReg).addReg(SrcReg);
1470     unsigned SrcReg = Allocation[ArgNo].Reg;
1471     Register DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[ArgNo].RC);
1603     Register SrcReg = getRegForValue(II->getOperand(0));
1604     if (SrcReg == 0)
1611         emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1621         emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1622         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1631         emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1643         emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1644         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1648         emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1651         emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1733     unsigned SrcReg = Reg + VA.getValNo();
1736     if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1764         SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1765         if (SrcReg == 0)
1772             TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1797   Register SrcReg = getRegForValue(Op);
1798   if (!SrcReg)
1803   updateValueMap(I, SrcReg);
1813   Register SrcReg = getRegForValue(Src);
1814   if (!SrcReg)
1829   if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1835 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1849   emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1854 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1860     emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1863     emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1869 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1874     return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1875   return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1878 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1896   emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1900 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1910     return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1911   return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1914 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1917   bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);