Lines Matching defs:CC
275 static bool canGuaranteeTCO(CallingConv::ID CC) { return false; }
278 static bool mayTailCallThisCC(CallingConv::ID CC) {
279 switch (CC) {
284 return canGuaranteeTCO(CC);
290 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
291 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
1151 // ??? How will this work if CC does not use registers for args passing?
1552 unsigned &CC) {
1580 CC = M68k::COND_VS;
1584 CC = M68k::COND_CS;
1588 CC = M68k::COND_VS;
1592 CC = M68k::COND_CS;
1598 CC = M68k::COND_VS;
1604 CC = M68k::COND_VS;
1634 unsigned CC;
1635 lowerOverflowArithmetic(Op, DAG, Result, CCR, CC);
1645 DAG.getConstant(CC, DL, MVT::i8), CCR);
1652 /// condition according to equal/not-equal condition code \p CC.
1653 static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC,
1669 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ;
1675 static SDValue LowerAndToBTST(SDValue And, ISD::CondCode CC, const SDLoc &DL,
1718 return getBitTestCondition(LHS, RHS, CC, DL, DAG);
1834 static SDValue LowerTruncateToBTST(SDValue Op, ISD::CondCode CC,
1845 CC, DL, DAG);
2132 SDValue M68kTargetLowering::LowerToBTST(SDValue Op, ISD::CondCode CC,
2136 return LowerAndToBTST(Op, CC, DL, DAG);
2138 return LowerTruncateToBTST(Op, CC, DL, DAG);
2149 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2157 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2158 if (SDValue NewSetCC = LowerToBTST(Op0, CC, DL, DAG)) {
2168 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2174 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
2187 if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2189 ISD::CondCode NewCC = ISD::GlobalISel::getSetCCInverse(CC, true);
2194 return DAG.getSetCC(DL, VT, Xor, DAG.getConstant(0, DL, MVT::i1), CC);
2199 unsigned M68kCC = TranslateM68kCC(CC, DL, IsFP, Op0, Op1, DAG);
2217 M68k::CondCode CC = TranslateIntegerM68kCC(cast<CondCodeSDNode>(Cond)->get());
2229 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
2266 SDValue CC;
2333 CC = Cond.getOperand(0);
2349 CC = DAG.getConstant(CCode, DL, MVT::i8);
2362 CC = NewSetCC.getOperand(0);
2370 CC = DAG.getConstant(M68k::COND_NE, DL, MVT::i8);
2379 unsigned CondCode = CC->getAsZExtVal();
2404 DAG.getNode(M68kISD::CMOV, DL, T1.getValueType(), T2, T1, CC, Cond);
2422 SDValue Ops[] = {Op2, Op1, CC, Cond};
2455 SDValue CC;
2485 CC = Cond.getOperand(0);
2494 switch (CC->getAsZExtVal()) {
2515 CC = DAG.getConstant(CCode, DL, MVT::i8);
2527 CC = Cond.getOperand(0).getOperand(0);
2529 Dest, CC, Cmp);
2530 CC = Cond.getOperand(1).getOperand(0);
2545 CC = DAG.getConstant(CCode, DL, MVT::i8);
2559 Dest, CC, Cmp);
2563 CC = DAG.getConstant(CCode, DL, MVT::i8);
2576 CC = DAG.getConstant(CCode, DL, MVT::i8);
2590 CC = NewSetCC.getOperand(0);
2599 CC = DAG.getConstant(MxCond, DL, MVT::i8);
2602 return DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain, Dest, CC,
3046 bool M68k::isCalleePop(CallingConv::ID CC, bool IsVarArg, bool GuaranteeTCO) {
3047 return CC == CallingConv::M68k_RTD && !IsVarArg;
3156 M68k::CondCode CC = M68k::CondCode(MI.getOperand(3).getImm());
3157 M68k::CondCode OppCC = M68k::GetOppositeBranchCondition(CC);
3168 (NextMIIt->getOperand(3).getImm() == CC ||
3238 unsigned Opc = M68k::GetCondBranchFromCond(CC);
3461 SDValue CC =
3464 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
3465 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
3516 SDValue CC =
3519 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
3520 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
3559 /// Optimize a CCR definition used according to the condition code \p CC into
3560 /// a simpler CCR value, potentially returning a new \p CC and replacing uses
3562 static SDValue combineSetCCCCR(SDValue CCR, M68k::CondCode &CC,
3565 if (CC == M68k::COND_CS)
3576 M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(0));
3580 if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget))
3581 return getSETCC(CC, Flags, DL, DAG);
3588 M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(2));
3594 if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget)) {
3595 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
3702 CCAssignFn *M68kTargetLowering::getCCAssignFn(CallingConv::ID CC, bool Return,