Lines Matching defs:And

92                          const MachineInstr &Sel, const MachineInstr &And) {
93   SlotIndex AndIdx = LIS->getInstructionIndex(And).getRegSlot();
131   auto *And =
133   if (!And || And->getOpcode() != AndOpc ||
134       !And->getOperand(1).isReg() || !And->getOperand(2).isReg())
137   MachineOperand *AndCC = &And->getOperand(1);
141     AndCC = &And->getOperand(2);
144   } else if (And->getOperand(2).getReg() != Register(ExecReg)) {
148   auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, *MRI, LIS);
151       Cmp->getParent() != And->getParent())
184   if (isDefBetween(*TRI, LIS, CCReg, *Sel, *And))
199                     << *And);
202       BuildMI(MBB, *And, And->getDebugLoc(), TII->get(Andn2Opc),
203               And->getOperand(0).getReg())
206   MachineOperand &AndSCC = And->getOperand(3);
212   SlotIndex AndIdx = LIS->ReplaceMachineInstrInMaps(*And, *Andn2);
213   And->eraseFromParent();