Lines Matching defs:STM

203   const GCNSubtarget *STM = nullptr;
827     EltSize = AMDGPU::convertSMRDOffsetUnits(*LSO.STM, 4);
1157 bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM,
1163     return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3));
1175       return STM.hasScalarDwordx3Loads();
1221     if (!widthsFit(*STM, CI, Paired) || !offsetsCanBeCombined(CI, *STM, Paired))
1251     offsetsCanBeCombined(CI, *STM, Paired, true);
1313   if (STM->ldsRequiresM0Init())
1319   if (STM->ldsRequiresM0Init())
1386   if (STM->ldsRequiresM0Init())
1393   if (STM->ldsRequiresM0Init())
1598       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);
1641       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);
1719 static bool needsConstrainedOpcode(const GCNSubtarget &STM,
1723   return STM.isXNACKEnabled() &&
1748         needsConstrainedOpcode(*STM, CI.I->memoperands(), Width);
1770         needsConstrainedOpcode(*STM, CI.I->memoperands(), Width);
1792         needsConstrainedOpcode(*STM, CI.I->memoperands(), Width);
2155   if (!STM->hasFlatInstOffsets() || !SIInstrInfo::isFLAT(MI))
2229     static_cast<const SITargetLowering *>(STM->getTargetLowering());
2540   STM = &MF.getSubtarget<GCNSubtarget>();
2541   if (!STM->loadStoreOptEnabled())
2544   TII = STM->getInstrInfo();