Lines Matching defs:OpName
231 MachineBasicBlock::iterator InsertBefore, int OpName,
235 int OpName) const;
340 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm();
465 if (!AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr) &&
466 !AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr0))
700 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
703 TII.isMIMG(Opc) ? AMDGPU::OpName::srsrc : AMDGPU::OpName::rsrc;
835 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm();
839 int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset);
844 Format = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::format)->getImm();
851 CPol = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm();
860 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0) + J;
863 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::addr);
866 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sbase);
869 Opc, isVIMAGEorVSAMPLE ? AMDGPU::OpName::rsrc : AMDGPU::OpName::srsrc);
872 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset);
875 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr);
878 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr);
881 Opc, isVIMAGEorVSAMPLE ? AMDGPU::OpName::samp : AMDGPU::OpName::ssamp);
964 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe);
965 const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe);
971 unsigned OperandsToMatch[] = {AMDGPU::OpName::cpol, AMDGPU::OpName::d16,
972 AMDGPU::OpName::unorm, AMDGPU::OpName::da,
973 AMDGPU::OpName::r128, AMDGPU::OpName::a16};
1182 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) {
1185 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::vdata)) {
1188 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) {
1191 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) {
1194 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::sdata)) {
1259 MachineBasicBlock::iterator InsertBefore, int OpName,
1268 auto *Dest0 = TII->getNamedOperand(*CI.I, OpName);
1269 auto *Dest1 = TII->getNamedOperand(*Paired.I, OpName);
1290 int OpName) const {
1300 const auto *Src0 = TII->getNamedOperand(*CI.I, OpName);
1301 const auto *Src1 = TII->getNamedOperand(*Paired.I, OpName);
1333 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr);
1376 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdst, DestReg);
1409 TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr);
1411 TII->getNamedOperand(*CI.I, AMDGPU::OpName::data0);
1413 TII->getNamedOperand(*Paired.I, AMDGPU::OpName::data0);
1479 AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::dmask);
1496 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata, DestReg);
1522 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase));
1524 New.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset));
1528 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::sdst, DestReg);
1554 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr));
1562 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc))
1563 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))
1569 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata, DestReg);
1595 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr));
1606 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc))
1607 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))
1614 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata, DestReg);
1630 copyFromSrcRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata);
1638 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr));
1649 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc))
1650 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))
1675 if (auto *SAddr = TII->getNamedOperand(*CI.I, AMDGPU::OpName::saddr))
1679 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr))
1684 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdst, DestReg);
1700 copyFromSrcRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata);
1703 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr))
1706 if (auto *SAddr = TII->getNamedOperand(*CI.I, AMDGPU::OpName::saddr))
1952 copyFromSrcRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata);
1960 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr));
1969 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc))
1970 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))
2059 auto *Base = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
2062 TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset);
2113 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0);
2114 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1);
2128 Src0 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src0);
2129 Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1);
2170 if (TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm()) {
2176 MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
2236 TII->getNamedOperand(MINext, AMDGPU::OpName::offset)->getImm())
2240 *TII->getNamedOperand(MINext, AMDGPU::OpName::vaddr);
2349 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz);