Lines Matching defs:ISD
708 {ISD::CTPOP, MVT::v2i64, 4},
709 {ISD::CTPOP, MVT::v4i32, 3},
710 {ISD::CTPOP, MVT::v8i16, 2},
711 {ISD::CTPOP, MVT::v16i8, 1},
712 {ISD::CTPOP, MVT::i64, 4},
713 {ISD::CTPOP, MVT::v2i32, 3},
714 {ISD::CTPOP, MVT::v4i16, 2},
715 {ISD::CTPOP, MVT::v8i8, 1},
716 {ISD::CTPOP, MVT::i32, 5},
720 if (const auto *Entry = CostTableLookup(CtpopCostTbl, ISD::CTPOP, MTy)) {
1645 // Bail due to missing support for ISD::STRICT_ scalable vector operations.
2733 int ISD = TLI->InstructionOpcodeToISD(Opcode);
2734 assert(ISD && "Invalid opcode");
2774 {ISD::FP_ROUND, MVT::bf16, MVT::f32, 1}, // bfcvt
2775 {ISD::FP_ROUND, MVT::bf16, MVT::f64, 1}, // bfcvt
2776 {ISD::FP_ROUND, MVT::v4bf16, MVT::v4f32, 1}, // bfcvtn
2777 {ISD::FP_ROUND, MVT::v8bf16, MVT::v8f32, 2}, // bfcvtn+bfcvtn2
2778 {ISD::FP_ROUND, MVT::v2bf16, MVT::v2f64, 2}, // bfcvtn+fcvtn
2779 {ISD::FP_ROUND, MVT::v4bf16, MVT::v4f64, 3}, // fcvtn+fcvtl2+bfcvtn
2780 {ISD::FP_ROUND, MVT::v8bf16, MVT::v8f64, 6}, // 2 * fcvtn+fcvtn2+bfcvtn
2785 BF16Tbl, ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT()))
2789 {ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1}, // xtn
2790 {ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1}, // xtn
2791 {ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1}, // xtn
2792 {ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1}, // xtn
2793 {ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 3}, // 2 xtn + 1 uzp1
2794 {ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1}, // xtn
2795 {ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2}, // 1 uzp1 + 1 xtn
2796 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1}, // 1 uzp1
2797 {ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1}, // 1 xtn
2798 {ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2}, // 1 uzp1 + 1 xtn
2799 {ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 4}, // 3 x uzp1 + xtn
2800 {ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1}, // 1 uzp1
2801 {ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 3}, // 3 x uzp1
2802 {ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 2}, // 2 x uzp1
2803 {ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 1}, // uzp1
2804 {ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 3}, // (2 + 1) x uzp1
2805 {ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 7}, // (4 + 2 + 1) x uzp1
2806 {ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2}, // 2 x uzp1
2807 {ISD::TRUNCATE, MVT::v16i16, MVT::v16i64, 6}, // (4 + 2) x uzp1
2808 {ISD::TRUNCATE, MVT::v16i32, MVT::v16i64, 4}, // 4 x uzp1
2811 {ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i8, 2},
2812 {ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i16, 2},
2813 {ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i32, 2},
2814 {ISD::TRUNCATE, MVT::nxv2i1, MVT::nxv2i64, 2},
2815 {ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i8, 2},
2816 {ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i16, 2},
2817 {ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i32, 2},
2818 {ISD::TRUNCATE, MVT::nxv4i1, MVT::nxv4i64, 5},
2819 {ISD::TRUNCATE, MVT::nxv8i1, MVT::nxv8i8, 2},
2820 {ISD::TRUNCATE, MVT::nxv8i1, MVT::nxv8i16, 2},
2821 {ISD::TRUNCATE, MVT::nxv8i1, MVT::nxv8i32, 5},
2822 {ISD::TRUNCATE, MVT::nxv8i1, MVT::nxv8i64, 11},
2823 {ISD::TRUNCATE, MVT::nxv16i1, MVT::nxv16i8, 2},
2824 {ISD::TRUNCATE, MVT::nxv2i8, MVT::nxv2i16, 0},
2825 {ISD::TRUNCATE, MVT::nxv2i8, MVT::nxv2i32, 0},
2826 {ISD::TRUNCATE, MVT::nxv2i8, MVT::nxv2i64, 0},
2827 {ISD::TRUNCATE, MVT::nxv2i16, MVT::nxv2i32, 0},
2828 {ISD::TRUNCATE, MVT::nxv2i16, MVT::nxv2i64, 0},
2829 {ISD::TRUNCATE, MVT::nxv2i32, MVT::nxv2i64, 0},
2830 {ISD::TRUNCATE, MVT::nxv4i8, MVT::nxv4i16, 0},
2831 {ISD::TRUNCATE, MVT::nxv4i8, MVT::nxv4i32, 0},
2832 {ISD::TRUNCATE, MVT::nxv4i8, MVT::nxv4i64, 1},
2833 {ISD::TRUNCATE, MVT::nxv4i16, MVT::nxv4i32, 0},
2834 {ISD::TRUNCATE, MVT::nxv4i16, MVT::nxv4i64, 1},
2835 {ISD::TRUNCATE, MVT::nxv4i32, MVT::nxv4i64, 1},
2836 {ISD::TRUNCATE, MVT::nxv8i8, MVT::nxv8i16, 0},
2837 {ISD::TRUNCATE, MVT::nxv8i8, MVT::nxv8i32, 1},
2838 {ISD::TRUNCATE, MVT::nxv8i8, MVT::nxv8i64, 3},
2839 {ISD::TRUNCATE, MVT::nxv8i16, MVT::nxv8i32, 1},
2840 {ISD::TRUNCATE, MVT::nxv8i16, MVT::nxv8i64, 3},
2841 {ISD::TRUNCATE, MVT::nxv16i8, MVT::nxv16i16, 1},
2842 {ISD::TRUNCATE, MVT::nxv16i8, MVT::nxv16i32, 3},
2843 {ISD::TRUNCATE, MVT::nxv16i8, MVT::nxv16i64, 7},
2846 {ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3},
2847 {ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3},
2848 {ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2},
2849 {ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2},
2850 {ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3},
2851 {ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3},
2852 {ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2},
2853 {ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2},
2854 {ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7},
2855 {ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7},
2856 {ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6},
2857 {ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6},
2858 {ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2},
2859 {ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2},
2860 {ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6},
2861 {ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6},
2864 {ISD::FP_EXTEND, MVT::f64, MVT::f32, 1}, // fcvt
2865 {ISD::FP_EXTEND, MVT::v2f64, MVT::v2f32, 1}, // fcvtl
2866 {ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 2}, // fcvtl+fcvtl2
2868 {ISD::FP_EXTEND, MVT::f32, MVT::f16, 1}, // fcvt
2869 {ISD::FP_EXTEND, MVT::f64, MVT::f16, 1}, // fcvt
2870 {ISD::FP_EXTEND, MVT::v4f32, MVT::v4f16, 1}, // fcvtl
2871 {ISD::FP_EXTEND, MVT::v8f32, MVT::v8f16, 2}, // fcvtl+fcvtl2
2872 {ISD::FP_EXTEND, MVT::v2f64, MVT::v2f16, 2}, // fcvtl+fcvtl
2873 {ISD::FP_EXTEND, MVT::v4f64, MVT::v4f16, 3}, // fcvtl+fcvtl2+fcvtl
2874 {ISD::FP_EXTEND, MVT::v8f64, MVT::v8f16, 6}, // 2 * fcvtl+fcvtl2+fcvtl
2876 {ISD::FP_EXTEND, MVT::f32, MVT::bf16, 1}, // shl
2877 {ISD::FP_EXTEND, MVT::f64, MVT::bf16, 2}, // shl+fcvt
2878 {ISD::FP_EXTEND, MVT::v4f32, MVT::v4bf16, 1}, // shll
2879 {ISD::FP_EXTEND, MVT::v8f32, MVT::v8bf16, 2}, // shll+shll2
2880 {ISD::FP_EXTEND, MVT::v2f64, MVT::v2bf16, 2}, // shll+fcvtl
2881 {ISD::FP_EXTEND, MVT::v4f64, MVT::v4bf16, 3}, // shll+fcvtl+fcvtl2
2882 {ISD::FP_EXTEND, MVT::v8f64, MVT::v8bf16, 6}, // 2 * shll+fcvtl+fcvtl2
2884 {ISD::FP_ROUND, MVT::f32, MVT::f64, 1}, // fcvt
2885 {ISD::FP_ROUND, MVT::v2f32, MVT::v2f64, 1}, // fcvtn
2886 {ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 2}, // fcvtn+fcvtn2
2888 {ISD::FP_ROUND, MVT::f16, MVT::f32, 1}, // fcvt
2889 {ISD::FP_ROUND, MVT::f16, MVT::f64, 1}, // fcvt
2890 {ISD::FP_ROUND, MVT::v4f16, MVT::v4f32, 1}, // fcvtn
2891 {ISD::FP_ROUND, MVT::v8f16, MVT::v8f32, 2}, // fcvtn+fcvtn2
2892 {ISD::FP_ROUND, MVT::v2f16, MVT::v2f64, 2}, // fcvtn+fcvtn
2893 {ISD::FP_ROUND, MVT::v4f16, MVT::v4f64, 3}, // fcvtn+fcvtn2+fcvtn
2894 {ISD::FP_ROUND, MVT::v8f16, MVT::v8f64, 6}, // 2 * fcvtn+fcvtn2+fcvtn
2896 {ISD::FP_ROUND, MVT::bf16, MVT::f32, 8}, // Expansion is ~8 insns
2897 {ISD::FP_ROUND, MVT::bf16, MVT::f64, 9}, // fcvtn + above
2898 {ISD::FP_ROUND, MVT::v2bf16, MVT::v2f32, 8},
2899 {ISD::FP_ROUND, MVT::v4bf16, MVT::v4f32, 8},
2900 {ISD::FP_ROUND, MVT::v8bf16, MVT::v8f32, 15},
2901 {ISD::FP_ROUND, MVT::v2bf16, MVT::v2f64, 9},
2902 {ISD::FP_ROUND, MVT::v4bf16, MVT::v4f64, 10},
2903 {ISD::FP_ROUND, MVT::v8bf16, MVT::v8f64, 19},
2906 {ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1},
2907 {ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1},
2908 {ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1},
2909 {ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1},
2910 {ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1},
2911 {ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1},
2914 {ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3},
2915 {ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3},
2916 {ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2},
2917 {ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3},
2918 {ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3},
2919 {ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2},
2922 {ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4},
2923 {ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2},
2924 {ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3},
2925 {ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2},
2928 {ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10},
2929 {ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4},
2930 {ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 10},
2931 {ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4},
2934 {ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 21},
2935 {ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 21},
2938 {ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4},
2939 {ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4},
2940 {ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2},
2941 {ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4},
2942 {ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4},
2943 {ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2},
2946 {ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 4},
2947 {ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 4},
2950 {ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1},
2951 {ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1},
2952 {ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1},
2953 {ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1},
2954 {ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1},
2955 {ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1},
2958 {ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2},
2959 {ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1},
2960 {ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1},
2961 {ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2},
2962 {ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1},
2963 {ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 1},
2966 {ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2},
2967 {ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2},
2968 {ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2},
2969 {ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2},
2972 {ISD::FP_TO_SINT, MVT::nxv2i64, MVT::nxv2f32, 1},
2973 {ISD::FP_TO_SINT, MVT::nxv2i32, MVT::nxv2f32, 1},
2974 {ISD::FP_TO_SINT, MVT::nxv2i16, MVT::nxv2f32, 1},
2975 {ISD::FP_TO_SINT, MVT::nxv2i8, MVT::nxv2f32, 1},
2976 {ISD::FP_TO_UINT, MVT::nxv2i64, MVT::nxv2f32, 1},
2977 {ISD::FP_TO_UINT, MVT::nxv2i32, MVT::nxv2f32, 1},
2978 {ISD::FP_TO_UINT, MVT::nxv2i16, MVT::nxv2f32, 1},
2979 {ISD::FP_TO_UINT, MVT::nxv2i8, MVT::nxv2f32, 1},
2982 {ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2},
2983 {ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2},
2984 {ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 2},
2985 {ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2},
2986 {ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2},
2987 {ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 2},
2990 {ISD::FP_TO_SINT, MVT::nxv2i64, MVT::nxv2f64, 1},
2991 {ISD::FP_TO_SINT, MVT::nxv2i32, MVT::nxv2f64, 1},
2992 {ISD::FP_TO_SINT, MVT::nxv2i16, MVT::nxv2f64, 1},
2993 {ISD::FP_TO_SINT, MVT::nxv2i8, MVT::nxv2f64, 1},
2994 {ISD::FP_TO_UINT, MVT::nxv2i64, MVT::nxv2f64, 1},
2995 {ISD::FP_TO_UINT, MVT::nxv2i32, MVT::nxv2f64, 1},
2996 {ISD::FP_TO_UINT, MVT::nxv2i16, MVT::nxv2f64, 1},
2997 {ISD::FP_TO_UINT, MVT::nxv2i8, MVT::nxv2f64, 1},
3000 {ISD::FP_TO_SINT, MVT::nxv4i64, MVT::nxv4f32, 4},
3001 {ISD::FP_TO_SINT, MVT::nxv4i32, MVT::nxv4f32, 1},
3002 {ISD::FP_TO_SINT, MVT::nxv4i16, MVT::nxv4f32, 1},
3003 {ISD::FP_TO_SINT, MVT::nxv4i8, MVT::nxv4f32, 1},
3004 {ISD::FP_TO_UINT, MVT::nxv4i64, MVT::nxv4f32, 4},
3005 {ISD::FP_TO_UINT, MVT::nxv4i32, MVT::nxv4f32, 1},
3006 {ISD::FP_TO_UINT, MVT::nxv4i16, MVT::nxv4f32, 1},
3007 {ISD::FP_TO_UINT, MVT::nxv4i8, MVT::nxv4f32, 1},
3010 {ISD::FP_TO_SINT, MVT::nxv8i16, MVT::nxv8f64, 7},
3011 {ISD::FP_TO_SINT, MVT::nxv8i8, MVT::nxv8f64, 7},
3012 {ISD::FP_TO_UINT, MVT::nxv8i16, MVT::nxv8f64, 7},
3013 {ISD::FP_TO_UINT, MVT::nxv8i8, MVT::nxv8f64, 7},
3016 {ISD::FP_TO_SINT, MVT::nxv4i32, MVT::nxv4f64, 3},
3017 {ISD::FP_TO_SINT, MVT::nxv4i16, MVT::nxv4f64, 3},
3018 {ISD::FP_TO_SINT, MVT::nxv4i8, MVT::nxv4f64, 3},
3019 {ISD::FP_TO_UINT, MVT::nxv4i32, MVT::nxv4f64, 3},
3020 {ISD::FP_TO_UINT, MVT::nxv4i16, MVT::nxv4f64, 3},
3021 {ISD::FP_TO_UINT, MVT::nxv4i8, MVT::nxv4f64, 3},
3024 {ISD::FP_TO_SINT, MVT::nxv8i16, MVT::nxv8f32, 3},
3025 {ISD::FP_TO_SINT, MVT::nxv8i8, MVT::nxv8f32, 3},
3026 {ISD::FP_TO_UINT, MVT::nxv8i16, MVT::nxv8f32, 3},
3027 {ISD::FP_TO_UINT, MVT::nxv8i8, MVT::nxv8f32, 3},
3030 {ISD::FP_TO_SINT, MVT::nxv8i64, MVT::nxv8f16, 10},
3031 {ISD::FP_TO_SINT, MVT::nxv8i32, MVT::nxv8f16, 4},
3032 {ISD::FP_TO_SINT, MVT::nxv8i16, MVT::nxv8f16, 1},
3033 {ISD::FP_TO_SINT, MVT::nxv8i8, MVT::nxv8f16, 1},
3034 {ISD::FP_TO_UINT, MVT::nxv8i64, MVT::nxv8f16, 10},
3035 {ISD::FP_TO_UINT, MVT::nxv8i32, MVT::nxv8f16, 4},
3036 {ISD::FP_TO_UINT, MVT::nxv8i16, MVT::nxv8f16, 1},
3037 {ISD::FP_TO_UINT, MVT::nxv8i8, MVT::nxv8f16, 1},
3040 {ISD::FP_TO_SINT, MVT::nxv4i64, MVT::nxv4f16, 4},
3041 {ISD::FP_TO_SINT, MVT::nxv4i32, MVT::nxv4f16, 1},
3042 {ISD::FP_TO_SINT, MVT::nxv4i16, MVT::nxv4f16, 1},
3043 {ISD::FP_TO_SINT, MVT::nxv4i8, MVT::nxv4f16, 1},
3044 {ISD::FP_TO_UINT, MVT::nxv4i64, MVT::nxv4f16, 4},
3045 {ISD::FP_TO_UINT, MVT::nxv4i32, MVT::nxv4f16, 1},
3046 {ISD::FP_TO_UINT, MVT::nxv4i16, MVT::nxv4f16, 1},
3047 {ISD::FP_TO_UINT, MVT::nxv4i8, MVT::nxv4f16, 1},
3050 {ISD::FP_TO_SINT, MVT::nxv2i64, MVT::nxv2f16, 1},
3051 {ISD::FP_TO_SINT, MVT::nxv2i32, MVT::nxv2f16, 1},
3052 {ISD::FP_TO_SINT, MVT::nxv2i16, MVT::nxv2f16, 1},
3053 {ISD::FP_TO_SINT, MVT::nxv2i8, MVT::nxv2f16, 1},
3054 {ISD::FP_TO_UINT, MVT::nxv2i64, MVT::nxv2f16, 1},
3055 {ISD::FP_TO_UINT, MVT::nxv2i32, MVT::nxv2f16, 1},
3056 {ISD::FP_TO_UINT, MVT::nxv2i16, MVT::nxv2f16, 1},
3057 {ISD::FP_TO_UINT, MVT::nxv2i8, MVT::nxv2f16, 1},
3060 {ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f32, 1},
3061 {ISD::FP_ROUND, MVT::nxv4f16, MVT::nxv4f32, 1},
3062 {ISD::FP_ROUND, MVT::nxv8f16, MVT::nxv8f32, 3},
3065 {ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f64, 1},
3066 {ISD::FP_ROUND, MVT::nxv4f16, MVT::nxv4f64, 3},
3067 {ISD::FP_ROUND, MVT::nxv8f16, MVT::nxv8f64, 7},
3070 {ISD::FP_ROUND, MVT::nxv2f32, MVT::nxv2f64, 1},
3071 {ISD::FP_ROUND, MVT::nxv4f32, MVT::nxv4f64, 3},
3072 {ISD::FP_ROUND, MVT::nxv8f32, MVT::nxv8f64, 6},
3075 {ISD::FP_EXTEND, MVT::nxv2f32, MVT::nxv2f16, 1},
3076 {ISD::FP_EXTEND, MVT::nxv4f32, MVT::nxv4f16, 1},
3077 {ISD::FP_EXTEND, MVT::nxv8f32, MVT::nxv8f16, 2},
3080 {ISD::FP_EXTEND, MVT::nxv2f64, MVT::nxv2f16, 1},
3081 {ISD::FP_EXTEND, MVT::nxv4f64, MVT::nxv4f16, 2},
3082 {ISD::FP_EXTEND, MVT::nxv8f64, MVT::nxv8f16, 4},
3085 {ISD::FP_EXTEND, MVT::nxv2f64, MVT::nxv2f32, 1},
3086 {ISD::FP_EXTEND, MVT::nxv4f64, MVT::nxv4f32, 2},
3087 {ISD::FP_EXTEND, MVT::nxv8f64, MVT::nxv8f32, 6},
3090 {ISD::BITCAST, MVT::nxv2f16, MVT::nxv2i16, 0},
3091 {ISD::BITCAST, MVT::nxv4f16, MVT::nxv4i16, 0},
3092 {ISD::BITCAST, MVT::nxv2f32, MVT::nxv2i32, 0},
3095 {ISD::BITCAST, MVT::nxv2i16, MVT::nxv2f16, 0},
3096 {ISD::BITCAST, MVT::nxv4i16, MVT::nxv4f16, 0},
3097 {ISD::BITCAST, MVT::nxv2i32, MVT::nxv2f32, 0},
3102 {ISD::ZERO_EXTEND, MVT::nxv16i16, MVT::nxv16i8, 2},
3103 {ISD::ZERO_EXTEND, MVT::nxv16i32, MVT::nxv16i8, 6},
3104 {ISD::ZERO_EXTEND, MVT::nxv16i64, MVT::nxv16i8, 14},
3105 {ISD::ZERO_EXTEND, MVT::nxv8i32, MVT::nxv8i16, 2},
3106 {ISD::ZERO_EXTEND, MVT::nxv8i64, MVT::nxv8i16, 6},
3107 {ISD::ZERO_EXTEND, MVT::nxv4i64, MVT::nxv4i32, 2},
3109 {ISD::SIGN_EXTEND, MVT::nxv16i16, MVT::nxv16i8, 2},
3110 {ISD::SIGN_EXTEND, MVT::nxv16i32, MVT::nxv16i8, 6},
3111 {ISD::SIGN_EXTEND, MVT::nxv16i64, MVT::nxv16i8, 14},
3112 {ISD::SIGN_EXTEND, MVT::nxv8i32, MVT::nxv8i16, 2},
3113 {ISD::SIGN_EXTEND, MVT::nxv8i64, MVT::nxv8i16, 6},
3114 {ISD::SIGN_EXTEND, MVT::nxv4i64, MVT::nxv4i32, 2},
3137 ConversionTbl, ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT()))
3141 {ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f16, 1}, // fcvtzs
3142 {ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f16, 1},
3143 {ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f16, 1}, // fcvtzs
3144 {ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f16, 1},
3145 {ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f16, 2}, // fcvtl+fcvtzs
3146 {ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f16, 2},
3147 {ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f16, 2}, // fcvtzs+xtn
3148 {ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f16, 2},
3149 {ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f16, 1}, // fcvtzs
3150 {ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f16, 1},
3151 {ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f16, 4}, // 2*fcvtl+2*fcvtzs
3152 {ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f16, 4},
3153 {ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f16, 3}, // 2*fcvtzs+xtn
3154 {ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f16, 3},
3155 {ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f16, 2}, // 2*fcvtzs
3156 {ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f16, 2},
3157 {ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f16, 8}, // 4*fcvtl+4*fcvtzs
3158 {ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f16, 8},
3159 {ISD::UINT_TO_FP, MVT::v8f16, MVT::v8i8, 2}, // ushll + ucvtf
3160 {ISD::SINT_TO_FP, MVT::v8f16, MVT::v8i8, 2}, // sshll + scvtf
3161 {ISD::UINT_TO_FP, MVT::v16f16, MVT::v16i8, 4}, // 2 * ushl(2) + 2 * ucvtf
3162 {ISD::SINT_TO_FP, MVT::v16f16, MVT::v16i8, 4}, // 2 * sshl(2) + 2 * scvtf
3167 FP16Tbl, ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT()))
3170 if ((ISD == ISD::ZERO_EXTEND || ISD == ISD::SIGN_EXTEND) &&
3192 if ((ISD == ISD::ZERO_EXTEND || ISD == ISD::SIGN_EXTEND) &&
3497 int ISD = TLI->InstructionOpcodeToISD(Opcode);
3499 switch (ISD) {
3503 case ISD::SDIV:
3522 case ISD::UDIV: {
3525 if (TLI->isOperationLegalOrCustom(ISD::MULHU, VT)) {
3548 if (TLI->isOperationLegalOrCustom(ISD, LT.second) && ST->hasSVE()) {
3556 {ISD::SDIV, MVT::v2i8, 5}, {ISD::SDIV, MVT::v4i8, 8},
3557 {ISD::SDIV, MVT::v8i8, 8}, {ISD::SDIV, MVT::v2i16, 5},
3558 {ISD::SDIV, MVT::v4i16, 5}, {ISD::SDIV, MVT::v2i32, 1},
3559 {ISD::UDIV, MVT::v2i8, 5}, {ISD::UDIV, MVT::v4i8, 8},
3560 {ISD::UDIV, MVT::v8i8, 8}, {ISD::UDIV, MVT::v2i16, 5},
3561 {ISD::UDIV, MVT::v4i16, 5}, {ISD::UDIV, MVT::v2i32, 1}};
3563 const auto *Entry = CostTableLookup(DivTbl, ISD, VT.getSimpleVT());
3601 case ISD::MUL:
3628 case ISD::ADD:
3629 case ISD::XOR:
3630 case ISD::OR:
3631 case ISD::AND:
3632 case ISD::SRL:
3633 case ISD::SRA:
3634 case ISD::SHL:
3639 case ISD::FNEG:
3649 case ISD::FADD:
3650 case ISD::FSUB:
3659 case ISD::FMUL:
3660 case ISD::FDIV:
3668 case ISD::FREM:
3706 int ISD = TLI->InstructionOpcodeToISD(Opcode);
3709 if (isa<FixedVectorType>(ValTy) && ISD == ISD::SELECT) {
3741 { ISD::SELECT, MVT::v2i1, MVT::v2f32, 2 },
3742 { ISD::SELECT, MVT::v2i1, MVT::v2f64, 2 },
3743 { ISD::SELECT, MVT::v4i1, MVT::v4f32, 2 },
3744 { ISD::SELECT, MVT::v4i1, MVT::v4f16, 2 },
3745 { ISD::SELECT, MVT::v8i1, MVT::v8f16, 2 },
3746 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 },
3747 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 },
3748 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 },
3749 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost },
3750 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost },
3751 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost }
3757 if (const auto *Entry = ConvertCostTableLookup(VectorSelectTbl, ISD,
3764 if (isa<FixedVectorType>(ValTy) && ISD == ISD::SETCC) {
3774 if (ValTy->isIntegerTy() && ISD == ISD::SETCC && I &&
4467 int ISD = TLI->InstructionOpcodeToISD(Opcode);
4468 assert(ISD && "Invalid opcode");
4470 switch (ISD) {
4471 case ISD::ADD:
4472 case ISD::AND:
4473 case ISD::OR:
4474 case ISD::XOR:
4475 case ISD::FADD:
4518 int ISD = TLI->InstructionOpcodeToISD(Opcode);
4519 assert(ISD && "Invalid opcode");
4530 {ISD::ADD, MVT::v8i8, 2},
4531 {ISD::ADD, MVT::v16i8, 2},
4532 {ISD::ADD, MVT::v4i16, 2},
4533 {ISD::ADD, MVT::v8i16, 2},
4534 {ISD::ADD, MVT::v4i32, 2},
4535 {ISD::ADD, MVT::v2i64, 2},
4536 {ISD::OR, MVT::v8i8, 15},
4537 {ISD::OR, MVT::v16i8, 17},
4538 {ISD::OR, MVT::v4i16, 7},
4539 {ISD::OR, MVT::v8i16, 9},
4540 {ISD::OR, MVT::v2i32, 3},
4541 {ISD::OR, MVT::v4i32, 5},
4542 {ISD::OR, MVT::v2i64, 3},
4543 {ISD::XOR, MVT::v8i8, 15},
4544 {ISD::XOR, MVT::v16i8, 17},
4545 {ISD::XOR, MVT::v4i16, 7},
4546 {ISD::XOR, MVT::v8i16, 9},
4547 {ISD::XOR, MVT::v2i32, 3},
4548 {ISD::XOR, MVT::v4i32, 5},
4549 {ISD::XOR, MVT::v2i64, 3},
4550 {ISD::AND, MVT::v8i8, 15},
4551 {ISD::AND, MVT::v16i8, 17},
4552 {ISD::AND, MVT::v4i16, 7},
4553 {ISD::AND, MVT::v8i16, 9},
4554 {ISD::AND, MVT::v2i32, 3},
4555 {ISD::AND, MVT::v4i32, 5},
4556 {ISD::AND, MVT::v2i64, 3},
4558 switch (ISD) {
4561 case ISD::FADD:
4581 case ISD::ADD:
4582 if (const auto *Entry = CostTableLookup(CostTblNoPairwise, ISD, MTy))
4585 case ISD::XOR:
4586 case ISD::AND:
4587 case ISD::OR:
4588 const auto *Entry = CostTableLookup(CostTblNoPairwise, ISD, MTy);