Lines Matching defs:SRA

992   assert((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) &&
993          "SRL or SRA node is required here!");
1058   case ISD::SRA: {
1978       if (Op0.getOpcode() == ISD::SRA && Op0.hasOneUse()) {
1986             return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRA, dl, VT,
2066   case ISD::SRA: {
2164           SDValue NewOp = TLO.DAG.getNode(ISD::SRA, dl, VT, DemandedOp0, Op1);
3653   case ISD::SRA:
4952         N0.getOpcode() == ISD::SRA && isa<ConstantSDNode>(N0.getOperand(1)) &&
6197     Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, SDNodeFlags::Exact);
6315   SDValue SRA =
6316       DAG.getNode(ISD::SRA, DL, VT, CMov, DAG.getConstant(Lg2, DL, VT));
6321     return SRA;
6323   Created.push_back(SRA.getNode());
6324   return DAG.getNode(ISD::SUB, DL, VT, Zero, SRA);
6483   Q = DAG.getNode(ISD::SRA, dl, VT, Q, Shift);
8196   // ISD::SRA/L nodes haven't. Insert an AND to be safe, it's usually optimized
8200   SDValue Tmp1 = IsSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8210     Tmp3 = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
8270   SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
9527       (!isOperationLegalOrCustom(ISD::SRA, VT) ||
9535       ISD::SRA, dl, VT, Op,
9632   unsigned ShiftOpc = IsSigned ? ISD::SRA : ISD::SRL;
10780   SDValue Shift = DAG.getNode(ISD::SRA, dl, VT, SumDiff,
10844       DAG.getNode(IsSigned ? ISD::SRA : ISD::SRL, dl, VT, Result, RHS);
10889   unsigned ShiftOpc = Signed ? ISD::SRA : ISD::SRL;
10944     // The high part is obtained by SRA'ing all but one of the bits of low
10948     HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, Shift);
10949     HiRHS = DAG.getNode(ISD::SRA, dl, VT, RHS, Shift);
11066         DAG.getNode(ISD::SRA, dl, WideVT, Res,
11112     SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, Lo,
11184     RHS = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, VT, RHS,
11331           DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL,
11375     SDValue Sign = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);