Lines Matching defs:LL

4759         return DAG.getSetCC(dl, VT, And, DAG.getConstant(0LL, dl, newVT), Cond);
7607                                     MulExpansionKind Kind, SDValue LL,
7627   // LL, LH, RL, and RH must be either all NULL or all set to a value.
7628   assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
7629          (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
7649   if (!LL.getNode() && !RL.getNode() &&
7651     LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LHS);
7655   if (!LL.getNode())
7662     if (MakeMUL_LOHI(LL, RL, Lo, Hi, false)) {
7679     if (MakeMUL_LOHI(LL, RL, Lo, Hi, true)) {
7701   if (!MakeMUL_LOHI(LL, RL, Lo, Hi, false))
7707     RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
7724   if (!MakeMUL_LOHI(LL, RH, Lo, Hi, false))
7768                           DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LL));
7780                                SDValue LL, SDValue LH, SDValue RL,
7785                            DAG, Kind, LL, LH, RL, RH);
7818                                             SDValue LL, SDValue LH) const {
7874     assert(!LL == !LH && "Expected both input halves or no input halves!");
7875     if (!LL)
7876       std::tie(LL, LH) = DAG.SplitScalar(N->getOperand(0), dl, HiLoVT, HiLoVT);
7884         PartialRem = DAG.getNode(ISD::AND, dl, HiLoVT, LL,
7888       LL = DAG.getNode(
7890           DAG.getNode(ISD::SRL, dl, HiLoVT, LL,
7904       Sum = DAG.getNode(ISD::UADDO, dl, VTList, LL, LH);
7908       Sum = DAG.getNode(ISD::ADD, dl, HiLoVT, LL, LH);
7909       SDValue Carry = DAG.getSetCC(dl, SetCCType, Sum, LL, ISD::SETULT);
7934     SDValue Dividend = DAG.getNode(ISD::BUILD_PAIR, dl, VT, LL, LH);
10879   SDValue LL = DAG.getNode(ISD::AND, dl, VT, LHS, Mask);
10882   SDValue T = DAG.getNode(ISD::MUL, dl, VT, LL, RL);
10899       DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::MUL, dl, VT, LL, RH), UL);