Lines Matching defs:LH

7608                                     SDValue LH, SDValue RL, SDValue RH) const {
7627   // LL, LH, RL, and RH must be either all NULL or all set to a value.
7628   assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
7629          (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
7689   if (!LH.getNode() && !RH.getNode() &&
7692     LH = DAG.getNode(ISD::SRL, dl, VT, LHS, Shift);
7693     LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
7698   if (!LH.getNode())
7708     LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
7710     Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
7731   if (!MakeMUL_LOHI(LH, RL, Lo, Hi, false))
7750   if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI))
7765     Next = DAG.getSelectCC(dl, LH, Zero, NextSub, Next, ISD::SETLT);
7780                                SDValue LL, SDValue LH, SDValue RL,
7785                            DAG, Kind, LL, LH, RL, RH);
7818                                             SDValue LL, SDValue LH) const {
7874     assert(!LL == !LH && "Expected both input halves or no input halves!");
7876       std::tie(LL, LH) = DAG.SplitScalar(N->getOperand(0), dl, HiLoVT, HiLoVT);
7892           DAG.getNode(ISD::SHL, dl, HiLoVT, LH,
7895       LH = DAG.getNode(ISD::SRL, dl, HiLoVT, LH,
7904       Sum = DAG.getNode(ISD::UADDO, dl, VTList, LL, LH);
7908       Sum = DAG.getNode(ISD::ADD, dl, HiLoVT, LL, LH);
7934     SDValue Dividend = DAG.getNode(ISD::BUILD_PAIR, dl, VT, LL, LH);
10890   SDValue LH = DAG.getNode(ShiftOpc, dl, VT, LHS, Shift);
10894       DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::MUL, dl, VT, LH, RL), TH);
10905   Hi = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::MUL, dl, VT, LH, RH),