Lines Matching defs:HiLoVT
7606 EVT HiLoVT, SelectionDAG &DAG,
7613 isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
7615 isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
7617 isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
7619 isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
7625 unsigned InnerBitSize = HiLoVT.getScalarSizeInBits();
7631 SDVTList VTs = DAG.getVTList(HiLoVT, HiLoVT);
7640 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, L, R);
7641 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R);
7650 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
7651 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LHS);
7652 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RHS);
7666 SDValue Zero = DAG.getConstant(0, dl, HiLoVT);
7691 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
7693 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
7695 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
7707 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
7708 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
7709 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
7710 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
7734 SDValue Zero = DAG.getConstant(0, dl, HiLoVT);
7747 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
7754 Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero,
7757 Hi = DAG.getNode(ISD::UADDO_CARRY, dl, DAG.getVTList(HiLoVT, BoolType), Hi,
7772 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
7774 Result.push_back(DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, Next));
7778 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
7784 N->getOperand(0), N->getOperand(1), Result, HiLoVT,
7817 EVT HiLoVT, SelectionDAG &DAG,
7837 HiLoVT.getScalarSizeInBits() == HBitWidth && "Unexpected VTs");
7846 if (!isOperationLegalOrCustom(ISD::MULHU, HiLoVT) &&
7847 !isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT))
7876 std::tie(LL, LH) = DAG.SplitScalar(N->getOperand(0), dl, HiLoVT, HiLoVT);
7884 PartialRem = DAG.getNode(ISD::AND, dl, HiLoVT, LL,
7885 DAG.getConstant(Mask, dl, HiLoVT));
7889 ISD::OR, dl, HiLoVT,
7890 DAG.getNode(ISD::SRL, dl, HiLoVT, LL,
7891 DAG.getShiftAmountConstant(TrailingZeros, HiLoVT, dl)),
7892 DAG.getNode(ISD::SHL, dl, HiLoVT, LH,
7894 HiLoVT, dl)));
7895 LH = DAG.getNode(ISD::SRL, dl, HiLoVT, LH,
7896 DAG.getShiftAmountConstant(TrailingZeros, HiLoVT, dl));
7901 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), HiLoVT);
7902 if (isOperationLegalOrCustom(ISD::UADDO_CARRY, HiLoVT)) {
7903 SDVTList VTList = DAG.getVTList(HiLoVT, SetCCType);
7906 DAG.getConstant(0, dl, HiLoVT), Sum.getValue(1));
7908 Sum = DAG.getNode(ISD::ADD, dl, HiLoVT, LL, LH);
7912 if (getBooleanContents(HiLoVT) ==
7914 Carry = DAG.getZExtOrTrunc(Carry, dl, HiLoVT);
7916 Carry = DAG.getSelect(dl, HiLoVT, Carry, DAG.getConstant(1, dl, HiLoVT),
7917 DAG.getConstant(0, dl, HiLoVT));
7918 Sum = DAG.getNode(ISD::ADD, dl, HiLoVT, Sum, Carry);
7926 // Perform a HiLoVT urem on the Sum using truncated divisor.
7928 DAG.getNode(ISD::UREM, dl, HiLoVT, Sum,
7929 DAG.getConstant(Divisor.trunc(HBitWidth), dl, HiLoVT));
7930 SDValue RemH = DAG.getConstant(0, dl, HiLoVT);
7948 std::tie(QuotL, QuotH) = DAG.SplitScalar(Quotient, dl, HiLoVT, HiLoVT);
7958 RemL = DAG.getNode(ISD::SHL, dl, HiLoVT, RemL,
7959 DAG.getShiftAmountConstant(TrailingZeros, HiLoVT, dl));
7960 RemL = DAG.getNode(ISD::ADD, dl, HiLoVT, RemL, PartialRem);
7963 Result.push_back(DAG.getConstant(0, dl, HiLoVT));